A great deal of research effort is focused on accelerating the development of 193-nm immersion lithography because
it appears to be the most suitable lithographic solution available for 65-nm-and-below semiconductor devices.
To realize a 193-nm immersion process, we must find ways to detect and analyze immersion specific defects, and
then establish processes that let us avoid such defects.
In this paper, we examine immersion specific defects and ways to detect and eliminate them in production processes.
Through comparison of dry exposure and immersion exposure processes, we have found that "bridges" and
"water-marks" are the most significant immersion specific defects using current developable top-coats. Although we
confirmed that the current solvent-removable top-coat process is better for avoiding immersion specific defects, we also
found that the defect density with a developable top-coat was still low enough for volume production.
We also investigated the causes of immersion specific defects and hypothesized that DI water permeation and the
local topology of the top-coat play an important role in the generation of immersion specific defects. To test whether this
was so, we evaluated the change in the top-coat film thickness by the quartz crystal microbalance technique. We
confirmed that top-coat swelling caused by water permeation into the top-coat film is a major cause of immersion
Immersion lithography has by far satisfied most expectations regarding its feasibility as the next lithographic
technique for the 65-nm node and below. To further advance 193-nm immersion lithography, a means of efficiently
controlling water as an immersion fluid and research and development concerning resist processes are necessary.
In 2004, Nikon Corporation introduced a 0.85 numerical aperture (NA) 193-nm immersion exposure tool that uses
water as the immersion liquid. This engineering evaluation tool (EET) is equipped with a highly efficient temperaturestabilized
water nozzle assembly. Selete Inc. in collaboration with Nikon Corporation has been evaluating the
performance and various characteristics of the EET while also investigating various photoresist and topcoat processes.
We selected three types of standard immersion processes that offered the best performance for our evaluation
purposes. A resolution limit of 70-nm half-pitch line-and-space (L/S) patterns has been confirmed. A 0.8-μm depth of
focus (DOF) was also verified for an 80-nm half-pitch L/S pattern. In addition, full wafer (WF) critical dimension (CD)
uniformity of less than 5 nm (3 sigma) has been demonstrated for a 90-nm half-pitch L/S pattern on a 300-mm wafer
(WF). After the implementation of various improvements to both the EET and the topcoat/resist processes, we have
achieved a total defect density of 0.23/cm<sup>2</sup>, and this defect level is low enough for pilot production.
Centerline phase-shifting mask (CL-PSM), which has narrow chromium lines at the boundaries of a μ-phase shifter, is promising as a resolution enhancement technology for random-pitch line patterns. We compared the performance of the CL-PSM in fabricating sub-45 nm lines with that of the chrome-less phase-shifting mask (CLM) in 157-nm lithography. The simulation results showed the CL-PSM is superior to the CLM in resolution and depth of focus (DOF), especially in small pitch patterns. We optimized the layouts of CL-PSM and the CLM to 40-nm-wide, 140-nm-pitch line patterns through the simulation. In exposure experiments with optimized masks, the CL-PSM resolved 40-nm-wide line patterns with a minimum pitch of 110 nm, while the resolvable minimum pitch was 130 nm for the CLM. The DOFs for 40-nm-wide, 140-nm-pitch lines were 200 and 80 nm with CL-PSM and CLM, respectively. Furthermore, we estimated the resolution limit of CL-PSM in hyper-NA 193-nm lithography, and showed a pitch of 100 nm would be achieved with a 1.4 NA optics.
The potential for extending the numerical aperture (NA) in order to develop devices beyond the 45-nm node has been investigated using a 157-nm microstepper exposure tool at 0.90NA (third generation) and verifying the resolution limit of several different resolution enhancement techniques. It was observed that with 157-nm lithography at 0.90NA a 60-nm line and space (L/S) and a 50-nm isolated line could be formed by using an attenuated phase shifting mask (Att-PSM), and that a 50-nm L/S and a 35-nm isolated line could be formed by using an alternating phase shifting mask (Alt-PSM). The influence of the flare for the same pattern sizes was more severe for the L/S pattern rather than isolated line. However, it was the most difficult to image an isolated line with an Att-PSM, which was limited with a tolerance to the flare of less than 1%. Furthermore, the requirement of more than 0.93 for lens NA was confirmed in order to fabricate half pitch 65-nm node device with Att-PSM and half pitch 45-nm node device with Alt-PSM. Results obtained in the pattern formation of 45-nm node with an Alt-PSM confirmed that a 35-nm line could be formed down to 140-nm pitch, a 40-nm line could be formed down to 135-nm pitch, and a 45-nm line could be formed down to 100-nm pitch. It has been demonstrated that 157-nm lithography could find application to half-pitch 65-nm and 45-nm node devices.