As semiconductor product development based on shrinkage continues, the accuracy and difficulty required for the model based optical proximity correction (MBOPC) is increasing. OPC simulation time, which is the most timeconsuming part of MBOPC, is rapidly increasing due to high pattern density in a layout and complex OPC model.
To reduce OPC simulation time, we attempt to apply graphic processing unit (GPU) to MBOPC because OPC process is good to be programmed in parallel. We address some issues that may typically happen during GPU-based OPC simulation in multi thread system, such as “out of memory” and “GPU idle time”. To overcome these problems, we propose a thread scheduling method, which manages OPC jobs in multiple threads in such a way that simulations jobs from multiple threads are alternatively executed on GPU while correction jobs are executed at the same time in each CPU cores. It was observed that the amount of GPU peak memory usage decreases by up to 35%, and MBOPC runtime also decreases by 4%. In cases where out of memory issues occur in a multi-threaded environment, the thread scheduler was used to improve MBOPC runtime up to 23%.
Overlay performance and control requirements have become crucial for achieving high yield and reducing rework process.
Increasing discrepancy between hardware solutions and overlay requirements, especially in sub-40nm dynamic random access
memory (DRAM) devices, motivates us to study process budgeting techniques and reasonable validation methods. In this paper, we
introduce a SMEM (Statistical process Margin Estimation Method) to design the DRAM cell architecture which considers critical
dimension (CD) and overlay variations in the perspectives of both cell architecture and manufacturability. We also proposed the
method to determine overlay specifications. Using the methodologies, we obtained successfully optimized sub-40 DRAM cells which
accurately estimated process tolerances and determined overlay specifications for all layers.
While predicting and removing of lithographic hot-spots are a matured practice in recent semiconductor industry, it is
one of the most difficult challenges to achieve high quality detection coverage and to provide designer-friendly fixing
guidance for effective physical design implementation. In this paper, we present an accurate hot-spot detection method
through leveling and scoring algorithm using weighted combination of image quality parameters, i.e., normalized image
log-slope (NILS), mask error enhancement factor (MEEF), and depth of focus (DOF) which can be obtained through
lithography simulation. Hot-spot scoring function and severity level are calibrated with process window qualification
results. Least-square regression method is used to calibrate weighting coefficients for each image quality parameter.
Once scoring function is obtained with wafer results, it can be applied to various designs with the same process. Using
this calibrated scoring function, we generate fixing guidance and rule for the detected hot-spot area by locating edge bias
value which can lead to a hot-spot free score level. Fixing guidance is generated by considering dissections information
of OPC recipe. Finally, we integrated hot-spot fixing guidance display into layout editor for the effective design
implementation. Applying hot-spot scoring and fixing method to memory devices of the 50nm node and below, we could
achieve a sufficient process window margin for high yield mass production.
Proc. SPIE. 6607, Photomask and Next-Generation Lithography Mask Technology XIV
KEYWORDS: Lithography, Data modeling, Data processing, Finite element methods, Design for manufacturing, Photomasks, Optical proximity correction, Critical dimension metrology, Photoresist processing, Process modeling
The adoption of the model-based OPC and RET does not guarantee enough process margin any more in the low
k1 lithography because potential patterning defects by layout-induced hot spots reduce common process window.
The introduction of the litho-friendly layout has faced practical limitation by the designers' short knowledge of the
lithography and its impact on the layout. In this paper, we develop a novel method based on restricted design rules
(RDR) and process window verification (PWV) to get rid of the layout-related process hot spots during the
physical layout design. Since RDR consists of simple design rules familiar to designers and PWV is implemented
on layout editor environment, this proposed method is easy to apply in the current design flow.
Since memory core layout is designed with typical and repeated patterns, the restriction of layout by design rule
enforcement is effective to remove hot spots in the core area. We develop a systematic RDR extraction method by
designing test patterns representing repeated memory core patterns by simple pattern matching technique.
1-dimensional (1D, simple line and space pattern) and 1.5-dimensional (1.5D, complicated line and space pattern)
test patterns are analyzed to take into account the printability. The 2-dimension (2D) test patterns split by contact
pad size are designed to consider the overlap margin between related layers. After removing the hot spots with
RDR violations on unit cell by auto-fixer, PWV is applied to detect the random hot spots located on peripheral
area. Analyzing CD difference between measurement and simulation according to variation of resist cutting plane
and focus, the optical model having physical meaning is generated. The resist model, which uses focus exposure
matrix (FEM) data within the process margin of memory cell, can represent the photo process variations
accurately. Implementing the proposed method based on RDR and PWV, depth of focus (DOF) of sub-60nm
memory device is improved by 50% compared with the result of original layout.
As the k1 factor of lithography process goes lower, model-based optical proximity correction (OPC) has become the most important step of post-tape-out data preparation for critical mask levels. To apply model-based OPC, a lithographic model with optical and resist parameters usually generated by a regression is required. It takes significant turn-around-time (TAT) to obtain the OPC model, normally more than 1 day per mask level. In this paper, we present an automatic and effective OPC model extraction method using the adaptive simulated annealing (ASA) algorithm. By applying this algorithm to extract the optimal model parameter values, we reduced the model parameter fitting time to less than 1 hour. We confirm the reliability and accuracy of the model generated by this method. With this newly developed automatic modeling method, we present a methodology to detect the critical failure on the wafer effectively that can occur by the focus variation during the lithography process. Generally, we sample only one set of measurement CD data taken under a controlled process condition with the best focus. Based on measurement data at the best focus, the in-house lithography simulator, FAITHTM, can generate simulated CD data for the multiple defocus levels without measurement data at the variable defocus levels. The multiple defocus models are built based on the simulated CD data and the automatic OPC modeling method makes the model buildings very fast. Finally, through the simulation of OPC result according to the multiple defocus models, we can verify or forecast the defocus effect before realistic patterning on wafers efficiently. We show the capability of weak point detection by this methodology on the 80nm DRAM devices with ArF photolithography.
The most important task in the OPC (optical proximity correction) process is to make a model database which can simulate optical behavior, while the characterization of resist development is still performed empirically. The previous approaches to lithography model generation heavily rely on 1 dimensional CD (critical dimension) measurements containing hundreds of features representing different sizes, shapes and pitches. Despite the huge amount of experiment data, there still can be a significant model error due to mismatching between measurement points and simulation points in 2 dimensional structures such as line ends, contact, and corners. Since the large number of data is required, it is quite natural that there require a huge computational effort to get the model. Our approach in this paper is based on the fitting model with 2D images, i.e., SEM image or a rigorous simulation image. It would not be an overstatement to say that a 2D wafer image is worth thousands of CD measurements. This approach is able to cover the symmetric as well as the non-symmetric patterns and prevents the threshold level from an inappropriate swing at the CTR (constant threshold resist) model. This paper aims to show how to extract the information of the wafer image, how to optimize the OPC modeling with quickness, and how to increase the modeling accuracy for the entire pattern. In addition, this paper shows the excellent agreement between the simulation image and the wafer image for the critical layout of the sub 70 nm technology node memory devices.
The quality of model-based OPC (MBOPC) depends on both modeling and correction accuracy. As the k1 process factor decreases and design complexity increases, the correction accuracy becomes more important. Especially, in case of high NA immersion lithography with strong off-axis illumination (OAI) such as dipole and cross-pole illumination, mask error enhancement factor (MEEF) and normalized intensity log-slope (NILS) vary seriously according to the pattern directions and shapes, so that the normal correction method, which uses the constant damping value, causes the divergence of correction and can hardly define optimum bias. Therefore, we developed design rule (D/R) constraints and new correction method to prevent the divergence and to reduce the OPC run time for sub-60nm device.
In this paper, D/R constraints derived from MEEF are introduced to reduce MEEF across the full chip. In addition, we propose new methods to achieve the global OPC convergence of low-k1 lithography by MEEF-based correction combined with proportion-integral-derivative (PID) controller. The PID controller can prevent the divergence because it considers the derivative term between EPEs (edge placement error) of previous and current iteration. Since MEEF-based correction uses the variable damping value derived from MEEF of each pattern fragment, it is effective for the convergence of the memory bit-line layer composed of the complicated 2D patterns. MEEF-based correction combined with PID controller merges the merits of each method and is found to be a stable correction method for k1 factor smaller than 0.27. Applying the proposed method, we could remove the process weak points having more than 20% CD variation caused by the divergence and achieve sufficient process margin for sub-60nm memory device. OPC run time is also reduced by 40% compared with the normal correction method.
Current model-based OPC methods are targeting the critical dimension and the fidelity of the design layout. These methods cannot suitably consider the process margin and reveal several problems below 70nm design layout with the low k1 process factor. Although litho-friendly layout methods have been introduced to improve the photolithography process margin, designing perfect litho-friendly layout is difficult because of the designer’s lacking of knowledge about the process and the relationship between the layers. Thus we have developed new OPC methods to increase the process margin for sub-70nm process. In this paper we propose new methods to generate the OPC-friendly layout from the original design by 1) rule-based retargeting, 2) model-based retargeting using NILS values, and 3) model-based retargeting by MEEF values. In addition, we have evaluated the post-processing treatment by NILS or MEEF values after the model-based OPC. The proposed OPC methods are effective for the memory bit line layer and metal layers, which are composed of the complicated 2-dimensional configuration and also have the advantage to compensate the model inaccuracy for the layout having non-periodic pattern structure. While the rule-based retargeting method requires high engineering cost to optimize the retargeting rule, the model-based retargeting method can be easily implemented into the conventional OPC process and do not need the extraction process of the retargeting rule which is not simple for the 2-dimensional patterns. Applying the model-based retargeting we could increase the DOF margin by 50% compared to the normal OPC method for sub-70nm memory device with ArF lithography. It is more effective to use these retargeting methods from the defocused OPC models.
As the lithography process approaches to the low k1 regime, the layout designers are forced to design the litho-friendly layout, which considers the process margin and mask error enhancement factor (MEEF). In addition, the lithography engineers are also impelled to optimize the optical proximity correction (OPC) rules at the full-chip level to eliminate the failures of the printed image on the wafer. Therefore, we have newly developed the simulation-based critical area extraction (CAE) and litho-friendly layout (LFL) design methodology based on the layout editor environment to design the litho-friendly layout and optimize the OPC rules. In this methodology, the critical areas of the full-chip level post-OPC layout, which have the lower process margin and larger critical dimension (CD) variation, are automatically extracted by evaluating the focus-exposure window, normalized image log-slope (NILS) and edge placement error (EPE). The extracted critical areas are sorted according to their causes of failures (i.e., notching, bridging, line-end shortening and larger CD variation, etc.). In order to maximize the process margin and minimize the MEEF at the full-chip level, layout designers and lithography engineers modify the original layout and optimize the OPC rules of the sorted critical areas based on the lithography simulator. The simulator uses the mask decomposition and selective simulation method to reduce the simulation time at the full-chip level. For the convenient CAE, process margin evaluation and layout optimization, the CAE function and lithography simulator are combined with the layout editor environment. Applying this methodology to the memory device of sub-90nm design rule, we have validated that our methodology can capture the pattern failures at the full-chip level and optimize both the original layout and OPC rules of those areas.
Sub-wavelength lithography has made the OPC (Optical Proximity Correction) technology one of the most precious commodities for the fabrication of semiconductor devices. Highly accurate gate CD (Critical Dimension) control and design rule shrinkage have become possible through the development of the OPC technology. Nevertheless, the device specifications require a more accurate gate CD control than the current OPC tools can cope with. For the model-based OPC to meet this tight CD specification, the model calibration process is very important. Current model-based OPC tools use their OPC models which usually cover the full-chip area with one universal model calibrated by comparing the empirical CD with the simulated CD of specially designed test patterns. Despite its safety, a single model for the full-chip OPC is not accurate for 2-dimensional patterns, and does not take into account the long-range effects of the patterning process such as flare noise or macro loading effect which is closely related to pattern density. In this work, we suggest a novel idea that applies the dual model to a single OPC process. We have found out that the CD trends of the patterns in the core and peripheral region of a memory chip differ from each other so that it is difficult to apply the same model for both regions. For the 110nm DRAM devices with 248nm lithography, we can reduce the gate CD variation up to 40% using the dual model OPC compared with the single model OPC. Since the dual model OPC uses two different models for a correction process, it should be carefully applied not to lose the conformity between the empirical process condition and the physical parameters of the models. The proposed dual model calibrated by the conservative modeling process reduces the gate CD variation by 50% compared with the single model OPC for a 90-nm DRAM device with 193nm lithography.
The k1 factor of the 65nm node device approaches to around 0.3 or even below because the device shrinking is much faster than the development speed of the high NA ArF scanner. Since the conventional model-based OPC (MBOPC) is only focused on patterning of the layout on the wafer as exactly same as the original design, it can hardly guarantee enough process margin in the low-k1 lithography regime. In this paper, illumination shape and retargeting rule of the multi-step OPC are optimized to improve the process margin of the 65nm node memory device. Sigma width and open angle of the dipole illumination is optimized to resolve the minimum pitch and to maintain the critical dimension (CD) uniformity. Even though the illumination is optimized and litho-friendly layout (LFL)  is applied, there is the process weak point caused by the device architecture. Applying the full-chip level verification, it is found that most of process weak points exist in isolated and semi-dense patterns of the core and peripheral region. The full-chip level verification uses the vector thin film model for the accurate resist image simulation of the high NA scanner. As the mask error enhancement factor (MEEF) is getting larger in the 65nm node device, the mask mean to target (MTT) rises as the dominant factor of the process margin. The NILS according to mask MTT variation is adopted as criterion for the process weak point extraction. Since the NILS of process weak point can be improved by the increasing pattern with, retargeting rules such as selective bias and pattern shift are applied. Under the dipole illumination, the NILS distributions of parallel and perpendicular patterns are different and the different retargeting rules are applied to them. Applying proposed illumination and multi-step OPC optimization to the 65nm node memory device, we have validated that our methodology can insure enough process margin for the volume production.