We have developed a new coded excitation technique where sigma-delta sampling and the corresponding single-bit pre-compression are utilized to reduce hardware complexity while improving signal-to-noise ratio (SNR) and penetration. From phantom studies, we have obtained a 10.03 dB SNR improvement with the proposed sigma-delta sampling-based coded excitation (SDS-CE) system compared to the conventional pulse-echo excitation method at the same voltage level. This improvement allows the necessary voltage level for the SDS-CE to be lowered to one sixth (e.g., ±10 V) of that for the conventional pulse-echo excitation method with the excitation voltage of ±60 V to achieve a comparable SNR and penetration depth. To evaluate the hardware complexity in the proposed method, the number of gates was estimated based on the 0.35-μm CMOS fabrication process. The proposed SDS-CE method can save 55.4%, 79.0% and 56.8% gates needed compared to the conventional pulse-echo method and the coded excitation method based on pre and post-compression, respectively. The proposed SDS-CE could lead to the integration of the transmitter and receiver circuitries into a single chip due to the improved SNR and reduced hardware complexity.