Model-based assist-feature (MBAF) placement has been shown to have considerable lithographic benefits vs. rule-based
assist-feature (RBAF) placement for advanced technology-node requirements. For very strong off-axis illumination,
MBAF-placement methods offer improved process window, especially for so-called forbidden pitch regions, and greatly
simplified tuning of AF-placement parameters. Historically, however, MBAF-placement methods had difficulties with
full-chip runtime, friendliness to mask manufacturing (e.g., mask rule checks or MRCs), and methods to ensure that
placed AFs do not print on-wafer. Therefore, despite their known limitations, RBAF-placement methods were still the
industry de facto solution through the 45 nm technology node. In this paper, we highlight recent manufacturability
advances for MBAFs by a detailed comparison of MBAF and RBAF methods. The MBAF method employed uses
Inverse Mask Technology (IMT) to optimize AF placement, size, shape, and software runtime, to meet the production
requirements of the 28 nm technology node and below. MBAF vs. RBAF results are presented for process window
performance, and MBAF vs. OPC results are presented for full-chip runtimes. The final results show that MBAF
methods have process-window advantages for technology nodes below 45 nm, with runtimes that are comparable to
Semiconductor manufacturers spend hundreds of millions of dollars and years of development time to create a new
manufacturing process and to design frontrunner products to work on the new process. A considerable percentage of this
large investment is aimed at producing the process design rules and related lithography technology to pattern the new
products successfully. Significant additional cost and time is needed in both process and design development if the
design rules or lithography strategy must be modified. Therefore, early and accurate prediction of both process design
rules and lithography options is necessary for minimizing cost and timing in semiconductor development.
This paper describes a methodology to determine the optimum design rules and lithography conditions with high
accuracy early in the development lifecycle. We present results from the 32nm logic node but the methodology can be
extended to the 22nm node or any other node. This work involves: automated generation of extended realistic logic test
layouts utilizing programmed teststructures for a variety of design rules; determining a range of optical illumination and
process conditions to test for each critical design layer; using these illumination conditions to create a extrapolatable
process window OPC model which is matched to rigorous TCAD lithography focus-exposure full chemically amplified
resist models; creating reticle enhancement technique (RET) recipes which are flexible enough to be used over a variety
of design rule and illumination conditions; OPC recipes which are flexible enough to be used over a variety of design
rule and illumination conditions; and OPC verification to find, categorize and report all patterning issues found in the
different design and illumination variations. In this work we describe in detail the individual steps in the methodology,
and provide results of its use for 32nm node design rule and process optimization.
At low k1 lithography and strong off-axis illumination, it is very hard to achieve edge-placement tolerances and 2-D
image fidelity requirements for some layout configurations. Quite often these layouts are within simple design rules
constraint for a given technology node. Evidently it is important to have these layouts included during early RET flow
development. Simple shrinkage from previous technology node is quite common, although often not enough. For logic
designs, it is hard to control design styles. Moreover for engineers in fabless design groups, it is difficult to assess the
manufacturability of their layouts because of the lack of understanding of the litho process.
Assist features (AF) are frequently placed according to pre-determined rules to improve lithography process window.
These rules are usually derived from lithographic models. Direct validation of AF rules is required at development
phase.To ensure good printability through process window, process aware optical proximity correction (OPC) recipes
were developed. Generally rules based correction is performed before model based correction. Furthermore, there are also
lots of other options and parameters in OPC recipes for an advanced technology, thus making it difficult to holistically
optimize performance of recipe bearing all these variables in mind.
In this paper we demonstrate the application of layout DOE in RET flow development. Layout pattern libraries are
generated using the Synopsys Test Pattern Generator (STPG), which is embedded in a layout tool (ICWB). Assessment
gauges are generated together with patterns for quick correction accuracy assessment. OPC verification through full
process is also deployed. Several groups of test pattern libraries for different applications are developed, ranging from
simple 1D pattern for process capability study and settings of process aware parameters to a full set of patterns for the
assessment of rules based correction, line end and corner interaction, active and poly interaction, and critical patterns for
contact coverage, etc.
Restrictive design rules (RDR) are commonly deployed to eliminate problematic layouts. We demonstrate RDR
evaluation and validation using our layout design of experiments (DOE) approach. This technique of layout DOE also
offers a simple and yet effective way to verify AF placement rules. For a given nominal layout features all possible assist
features are generated within the mask rules constraint using STPG. Then we run OPC correction and assess main feature
critical dimension (CD) at best and worst process condition in ICWB. Best assist feature placement rules are derived based
on minimum CD difference. The rules derived from this approach are not the same as those derived from the commonly
used method of least intensity variation.