Light-emitting diode (LED) is a liquid cold source light source that rapidly develops in recent years. The merits of high brightness efficiency, long duration, high credibility and no pollution make it satisfy our demands for consumption and natural life, and gradually replace the traditional lamp-house-incandescent light and fluorescent light. However, because of the high cost and unstable drive circuit, the application range is restricted. To popularize the applications of the LED, we focus on improving the LED driver circuit to change this phenomenon. Basing on the traditional LED drive circuit, we adopt pre-setup constant current model and introduce pulse width modulation (PWM) control method to realize adjustable 256 level-grays display. In this paper, basing on human visual characteristics and the traditional PWM control method, we propose a new PWM control timing clock to alter the duty cycle of PWM signal to realize the simple gamma correction. Consequently, the brightness can accord with our visual characteristics.
Designed a three-channel LED driver, realized the single-wire transmission of cascade signal between the drive IC of LED. Including the MCU digital interface, date register, clock synchronization, PWM grayscale adjustment circuit, as well as high voltage driver circuit for LED, etc… The driver control LED displaying 256 gray. Chip will generate synchronous sampling clock signals according to the received serial signals, when 24 bits dates have been received, the output pin begins to transport the dates followed-up which are automotive shaped to the input of the next chip. When the date receiving becomes low level that represent RESET, the red, green and blue channels will export different signals based on different input dates. Through the external MCU, it is realized the Separate luminance, and by connecting chips in series it achieved the control of outdoor big screen’ colorful display. The automatic shaping forward technique makes the number of chips cascading immune to the limitations of signal transmission, but only limited by the refresh speed.
Infrared focal plane array (IRFPA) is a key component in infrared system and thermal imaging devices, widely applied in military and civilian fields, with a huge market potential and prospects. IRFPA readout circuit technology and test technology in its research occupies an important position, related to the ability to accurately and efficiently obtain the IRFPA signal and the ability of IRFPA devices for accurate performance evaluation. This paper uses an IRFPA point-by-point bias calibration, through a series of accurate timing control signals to read and save the calibration data and external input, effectively increases the point-by-point bias control accuracy, and finally improves the quality of the output image.
Recent years witnessed that LEDs have been widely used in many consumer electronics and other areas. However, many applications require a large number of LED cascade drives. When LED driver IC drives cascaded LEDs, the cascade length is often limited because of the insufficient drive capability of the data clock. Once the technology of data clock regeneration is applied in LED driver chip, Signal drive capability is effectively enhanced by the data clock regeneration, thus the cascade length is greatly increased. After the algorithm of data clock regeneration is verified in Quartus II, the circuit and layout of LED driver are designed in Cadence using this technology. In product test, LED driver based on the data clock regeneration drives more than 2,000 points cascaded LEDs at 25 MHz clock. LED drivers with this technique are suitable for a variety of large-scale cascaded LEDs.
The Uncooled Focus Plane Array (UFPA) infrared detector is widely used in military and civil fields. With the features of small size and not being cooled, the Uncooled Infrared Focal Plane Array (UIRFPA) has become the focus in the current infrared thermal imaging research. A data acquisition system has been designed and implemented for measurement of the UIRFPA. The system includes driver module, acquisition module and signal processing module. The acquisition module based on virtual instrument can achieve high-speed, stable and accurate data acquisition. Meanwhile, combined with visual C+ + (VC) platform, the system realizes data acquisition and real time imaging. Through testing a 240×320 FPA using the test system, the superior performance of the device has been performed. In addition, the imaging effect has been enhanced by eliminating the bad pixels and proofreading the non-uniformity. A new test system for the test of UIRFPA and the exploration of the real-time correction imaging system is presented.
This paper designs a ramp generating circuit using for uncooled infrared focal plane arrays (UIRFPA). Compared with the basic ramp generator, the new generator is highly adjustable, easy to operate, and adaptable. By adjusting the total current of the charging circuit, it can realize the ramp wave upper point and slope of the modulation. Current mirror as the discharge load, it can adjust the ramp lower point, and controllable capability. By adjusting accuracy and swing, the new ramp generator for UIRFPA provides a way to adapt to the strength of the infrared scene to control the infrared signal accuracy. Simulation results show that the ramp output swing can be adjusted from 1 V to 4.5 V, a maximum Integral nonlinearity (INL) of 400 µV, a slope distortion lower than 0.01%, linearity higher than 13 bits for the new ramp generator (considering a 4 V input range). At the same time, its good temperature performance shows that the maximum difference of the output voltage is 50 mV in a variety of environments (243 K ~ 333 K). Besides, this circuit has been successfully applied to the infrared system.
Infrared detection technology plays a more and more important role in military and business. Uncooled infrared focal plane array (UFPA) is a kind of thermal detector, which detects the infrared radiation of target through the microbolometer’s photoelectric conversion. Based on the thermal model of UFPA, stable and accordant substrate temperature of microbolometer array is extreme important to improve the UFPA’s noise performance. After researching the effects of substrate temperature act on UFPA’s noise performance and responsivity, a low noise data capture system with TEC controller for UFPA is designed. And a 320x240 microbolometer array’s noise is tested with this system. With the TEC controller, the substrate temperature fluctuates at a margin of only 0.006 ºC. The test result shows that a 12.1% decrease in RMS noise, a 14.5% decrease in FPN noise and improvement of responsivity non-uniformity over time have been obtained after using TEC controller in UFPA.
This paper presents a new Read_out IC (ROIC) that uses two shared capacitances for integral and sampling. At similar power consumption and chip area, this ROIC architecture achieves a higher frame rate compared with the conventional architecture. A 384×288 uncooled microbolometer focal plane array (FPA) based on the proposed circuit was implemented on silicon using a 0.5 μm CMOS technology. Measurements show the proposed architecture enables the frame rate increase of 6.8% using the same master clock.
We propose a novel CMOS readout structure without sample and hold (SH) circuit for uncooled microbolometers. In this
readout circuit, all the pixels in one row can be integrated simultaneously, and the readout integrated circuit (ROIC) area
can be reduced by as much as 30%. Moreover, a single capacitor implementation of both capacitive transimpedance
amplifier (CTIA) and correlated double sampling (CDS) is utilized to improve noise performance. An experimental
40x30 ROIC chip has been designed and fabricated with 0.5 μm CMOS technology. The test results show that the ROIC
has good linearity with 260μV RMS total output noise voltage and 1800x650 μm<sup>2</sup> total circuit area.