Traditional mask critical dimension (CD) disposition systems with only one or two targets is being challenged by the new requirements from mask-users as the wafer process control becomes more complicated in the newer generation of technologies. Historically, the mask shop does not necessarily measure and disposition off the same kind of CD structures that wafer fabs do. Mask disposition specifications and structures come from the frame-design and the tapeout, while wafer-level CD dispositions are mainly based on the historical process window established per CD-skew experiments and EOL (end of line) yield. In the current high volume manufacturing environment, the mask CDs are mainly dispositioned off their mean-to-target (MTT) and uniformity (6sigma) on one or two types of pre-determined structures. The disposition specification is set to ensure the printed mask will meet the design requirements and to ensure minimum deviation from them. The CD data are also used to adjust the dose of the mask exposure tools to control CD MTT. As a result, the mask CD disposition automation system was built to allow only one or two kinds of targets at most. In contrast, wafer-fabs measure a fairly wide range of different structures to ensure their process is on target and in control. The number of such structures that are considered critical is increasing due the growing complexity of the technology. To fully comprehend the wafer-level requirements, it is highly desirable to align the mask CD sample site and disposition to be the same as that of the wafer-fabs, to measure the OPC (optical proximity correction) structures or equivalent whenever possible, and to establish the true correlation between mask CD measurements vs. wafer CD measurement. In this paper, the development of an automated multiple-target mask CD disposition system with the goal of enabling new sampling strategy is presented. The pros and cons of its implementation are discussed. The new system has been inserted in the production of Intel's 65 nm technologies and has become the POR (plan of record) for the future technologies that are being developed.
Alternating Phase Shift Mask (APSM) Technology has been developed and successfully implemented for the poly gate of 65nm node Logic application at Intel. This paper discusses the optimization of the mask design rules and fabrication process in order to enable high volume manufacturability. Intel's APSM technology is based on a dual sided trenched architecture. To meet the stringent OPC requirements associated with patterning of narrow gates required for the 65nm node, Chrome width between the Zero and Pi aperture need to be minimized. Additionally, APSM lithography has an inherently low MEEF that furthermore, drives a narrower Chrome line as compared to the Binary approach. The double sided trenched structure with narrow Chrome lines are mechanically vulnerable and prone to damage when exposed to conventional mask processing steps. Therefore, new processing approaches were developed to minimize the damage to the patterned mask features. For example, cleaning processes were optimized to minimize Chrome & quartz damage while retaining the cleaning effectiveness. In addition, mask design rules were developed which ensured manufacturability. The narrow Chrome regions between the zero and Pi apertures severely restrict the tolerance for the placement of the second level resists edges with respect to the first level. UV Laser Writer based resist patterning capability, capable of providing the required Overlay tolerance, was developed, An AIMS based methodology was used to optimize the undercut and minimize the aerial image CD difference between the Zero and Pi apertures.
Alternating phase shift mask (APSM) techniques help bridge the significant gap between the lithography wavelength and the patterning of minimum features, specifically, the poly line of 35 nm gate length (1x) in Intel's 65 nm technology. One of key steps in making APSM mask is to pattern to within the design tolerances the 2nd level resist so that the zero-phase apertures will be protected by the resist and the pi-phase apertures will be wide open for quartz etch. The ability to align the 2nd level to the 1st level binary pattern, i.e. the 2nd level overlay capability is very important, so is the capability of measuring the overlay accurately. Poor overlay could cause so-called the encroachment after quartz etch, producing undesired quartz bumps in the pi-apertures or quartz pits in the zero-apertures. In this paper, a simple, low-cost optical setup for the 2nd level DC (develop check) overlay measurements in the high volume manufacturing (HVM) of APSM masks is presented. By removing systematic errors in overlay associated with TIS and MIS (tool-induced shift and Mask-process induced shift), it is shown that this setup is capable of supporting the measurement of DC overlay with a tolerance as small as +/- 25 nm. The outstanding issues, such as DC overlay error component analysis, DC - FC (final check) overlay correlation and the overlay linearity (periphery vs. indie), are discussed.
Phase shift mask (PSM) applications are becoming essential for addressing the lithography requirements of the 65 nm technology node and beyond. Many mask writer properties must be under control to expose the second level of advanced PSM: second level alignment system accuracy, resolution, pattern fidelity, critical dimension (CD) uniformity and registration. Optical mask writers have the advantage of process simplicity for this application, as they do not require a discharge layer. This paper discusses how the mask writer properties affect the error budget for printing the second level. A deep ultraviolet (DUV) mask writer with a spatial light modulator (SLM) is used in the experimental part of the paper. Partially coherent imaging optics at the 248 nm wavelength provide improved resolution over previous systems, and pattern fidelity is optimized by a real-time corner enhancement function. Lithographic performance is compared to the requirements for second level exposure of advanced PSM. The results indicate sufficient capability and stability for 2nd level alternating PSM patterning at the 65 nm and 45 nm nodes.
A new chrome etch system was acquired and implemented to manufacture 65 nm node critical level masks. The etch performance of FEP 171, ZEP 7000, NEB 22, and REAP 200 resist systems in this new chrome etch system was evaluated. The critical dimension (CD) uniformity, etch bias, and etch linearity of this new etch system relative to the older generation etch system is presented. Implementation of the new etch system resulted in a 40-60 nm reduction in etch bias with no degrade in CD uniformity performance. In addition, it was found that the etch contribution to CD linearity was reduced by 50%. Detailed characterization of both macroloading and microloading etch effects was performed and showed substantial improvement relative to the previous generation etch system. The change in chrome etch rate as a function of etch area was reduced by 50%, improving mean to target CD performance on new designs. Implementation of the new etch system has enabled achievement of CD and defect density performance requirements for 65 nm node mask manufacturing. The results presented in this paper were collected during the process development phase and are not necessarily representative of the final optimized process.
Mask manufacturing becomes more complicated with each technology generation. The number of tools and processing steps is increasing while the feature geometries and substrate materials are becoming more difficult to process. At the same time, the market demands new product introductions at a faster rate than ever before. The only way to meet all of these challenges is through faster yield (critical dimensions, defects, registration) learning. However, the rate of technology development for manufacturing has far outpaced the development of yield learning solutions. Spreadsheet-based learning tools are severely limited in their ability to handle the complex hierarchical data, and often there is not enough data available for a meaningful statistical analysis. We have deployed a novel application that greatly enhances our ability to perform commonality studies, which are a key element of yield learning. This application is based on treemapping technology, which takes advantage of the human eye's ability to detect subtle changes. Here, data is represented graphically on a two-dimensional screen. However, additional dimensions are included on the same plot through the use of size, color, and hierarchical nesting. This has enabled us to be more sophisticated in our approaches to yield learning through visualizing multidimensional correlations. In addition to improving our ability to perform commonality studies, the tool has also been used for process stability analysis, hold and excursion analysis, and several other manufacturing and engineering applications.
We present a systematic study of compositional and doping effects in Bi2Sr2CaCu2Oy high-Tc superconductors performed with photoemission spectroscopy. The study has been extended to Y-doping and I-intercalation of Bi-2212 high quality single crystals. The main results is that each type of dopant affects the crystal composition in its own way. Yttrium affects the Ca and Sr planes, producing a charge transfer into the CuO planes. For I-doping, we find that the main effect is a change in the interplanar distance, but X-ray Photoemission Spectroscopy (XPS) allows to see that the decrease of the over-doping of copper planes (hole doping). We performed also a comparative study by Angle Resolved Ultraviolet Photoemission Spectroscopy (ARUPS) between this sample and an oxygen annealed specimen. XPS Cu2p core level data establish that the hole concentration in the CuO2 planes is essentially the same for these two kinds of samples. ARUPS measurements show that electronic structure of the normal states near the Fermi level has been strongly affected by iodine intercalation.