As the VLSI feature size has already decreased below lithographic wavelength, the printability problem due to strong
diffraction effects poses a serious threat to the progress of VLSI technology. A circuit layout with poor printability implies
that it is difficult to make the printed features on wafers follow designed shapes without distortions. The development
of Resolution Enhancement Techniques (RET) can alleviate the printability problem but cannot reverse the trend of deterioration.
Moreover, over-usage of RET may dramatically increase photo-mask cost and increase the cycle time for
volume production. Thus, there is a strong demand to consider the sub-wavelength printability problem in circuit layout
designs. However, layout printability optimization should not degrade circuit timing performance. In this paper, we introduce
a wire sizing and spacing method to improve wire printability with minimal adverse impact on interconnect timing
performance. A new printability model is proposed to handle partially coherent illuminations. The difficult problem of
printability optimization due to its multimodal nature is handled with a sensitivity based heuristic in timing aware fashion.
Lithographic simulation results show that our approach can improve the printability in term of EPE (Edge Placement Error)
by 20%-40% without violating timing, wire width and spacing constraints.
In sub-wavelength lithography, light field Alt-PSM (Alternating Phase Shifting Mask) is an essential technology for poly layer printability. In a standard cell based design, the problem of obtaining Alt-PSM compliance for an individual cell layout has been solved well . However, placing Alt-PSM compliant cells together can not guarantee Alt-PSM compliance of the entire chip/block layout due to phase interactions among adjacent cells. A simple solution to this Alt-PSM composability problem is to wrap blank area around each cell, which is very inefficient on chip area usage. In this paper, we formulate the composability problem as a graph model and propose a polynomial time optimal algorithm to achieve Alt-PSM composability with the least impact on cell layout.