Reverse-tone step and flash imprint lithography SFIL-R
shows promise as a cost-efficient, high-resolution patterning technique;
however, the generation of satisfactory patterns requires the successful
application of a planarizing topcoat over topography through spincoating.
Photopolymerizable nonvolatile fluids are ideal topcoat materials because
they planarize better than volatile fluids during spincoating and
can continue to level after spincoating. Fluid mechanics analyses indicate
that complete planarization using capillary force is slow. Therefore,
defining the acceptable or critical degree of planarization DOPcrit becomes
necessary. Finite difference simulation of the spincoat and postspin
leveling processes was used to determine the planarization time for
various topographic and material property combinations. A new material,
Si-14, was designed to have ideal planarization characteristics low
viscosity-15.1 cP; low shrinkage-5.1% and satisfy SFIL-R processing
requirements oxygen etch resistance-33 wt% silicon, photocurable
and was used to validate our models through profilometry and interferometry
experiments. During spincoating, minimizing the spin speed generates
more planar films; however, this increases the spin time. To rectify
this problem, a two-stage spincoating process-a first step with high spin
speeds to achieve the target thickness quickly and a second step with
low spin speeds to improve planarization-was proposed and experimentally
Step and flash imprint lithography (SFIL) is low cost, high resolution patterning process and has found its way into a multitude of front end of the line (FEOL) and back end of the line (BEOL) applications. SFIL-R, a reverse tone variant of SFIL, and imprintable dielectrics are examples of such applications, and both require the design of specialized, silicon-based materials. Polyhedral oligomeric silsesquioxane (POSS) liquids were modified through a dual functionalization strategy to introduce photosensitive acrylate and thermally curable benzocyclobutane (BCB) groups to the molecule. The optimal functional group ratio was observed to be 3:5 acrylate to BCB, and the result was an imprintable dielectric with good mechanical properties and minimal post-exposure shrinkage. Thermal gravimetric analysis (TGA) revealed good thermal stability with minimal mass loss under annealing conditions of 400°C for 2 hours. Si-14 was designed to be a non-volatile, etch-resistant planarization layer for SFIL-R application. A polydimethylsiloxane (PDMS) derivative was modified to introduce acrylate functional groups and side branching for photosensitivity and low viscosity, respectively. Characterization of the material showed ideal planarization characteristics - low volatility (0.77 Torr at 25°C), low viscosity (15.1 cP), and minimal post-exposure shrinkage (5.1%).
Modern integrated circuit fabrication uses the dual damascene process to create the copper
interconnects in the Back End of the Line (BEOL) processing. The number of wiring levels is
increasing to eight or more in advanced microprocessors, and the complexity and cost of the
BEOL processes is growing rapidly. An approach to dual damascene processing using Step and
Flash Imprint Lithography (S-FIL®) in conjunction with Sacrificial Imprint Materials (SIM) offers the
ability to pattern two levels of interconnect structures simultaneously. By using a multi-level
imprint template built with both the via and trench structures, one imprint lithography step can
produce the same structures as two photolithography steps, greatly reducing the number of
patterning process steps in the BEOL layers. This paper presents progress in formulation of new
sacrificial imprint materials and the development of S-FIL and etch processes to incorporate the
SIM strategy. The SIM is formulated as a two-component system, with a tunable etch rate
adjusted by the ratio of the monomer and cross-linker components. High quality imprints were
produced with a multi-level template on wafers with blank films of black diamond® dielectric
material. The quality of the multi-level pattern transfer from the SIM into black diamond was
Understanding the dynamics of thin film planarization over topography is a key issue in the reverse-tone step and flash imprint lithography (SFIL-R) process. Complete planarization of a film over large, isolated topography poses an enormous challenge, since the driving force for planarization, the capillary pressure, continuously weakens as the film becomes more planar. For SFIL-R, only a specific degree of planarization (DOP) needs to be achieved before pattern transfer is possible. This paper presents the derivation of an inequality statement describing the required extent of planarization for successful pattern transfer. To observe how this critical DOP value (DOPcrit), and its corresponding leveling time (Tcrit) vary with materials and topographic properties, finite difference simulation was utilized to model planarization of a thin film over isolated topography after the spincoating process. This model was verified experimentally for various film thickness to substrate height ratios using interferometry to monitor silicon oil planarization over isolated trenches and lines. Material and topographic parameters were shown to not have a dramatic impact on DOPcrit; however, the critical leveling time increased considerably at DOPcrit values above 60 percent.
The dual damascene process used to generate copper interconnects requires many difficult processing steps. Back End Of Line (BEOL) processing using Step and Flash Imprint Lithography (SFIL) on a directly patternable dielectric material can dramatically reduce the number of processing steps. By using multi-level SFIL rather than photolithography, two levels of interconnect structure (trench and corresponding via) can be patterned simultaneously. In addition, the imprinted material can be a imprintable dielectric precursor rather than a resist, further reducing the total number of steps in the dual damascene process. This paper presents progress towards integrating multi-level SFIL into a copper CMP process flow at ATDF, Inc. in Austin, Texas. Until now, work has focused on multi-level imprint process development. This report focuses on the development of new imprintable dielectric precursors for use with the dual damascene imprint process. SFIL compatible dielectric precursors were synthesized and characterized for integration into the ATDF copper CMP process flow. SFIL requires properties not found in currently available semiconductor dielectrics such as low viscosity and rapid photo-induced polymerization. Inorganic/organic hybrid materials derived from sol-gel chemistry and polyhedral oligomeric silsesquioxane (POSS) structures show promise for this application. The properties of three different dielectric layers are compared. The viability of each material as an interlayer dielectric is discussed and the results of multi-level patterning, metal fill, and polish are shown.
Advanced microprocessors require several (eight or more) levels of wiring to carry signal and power from transistor to transistor and to the outside world. Each wiring level must make connection to the levels above and below it through via/contact layers. The dual damascene approach to fabricating these interconnected structures creates a wiring level and a via level simultaneously, thereby reducing the total number of processing steps. However, the dual damascene strategy (of which there are several variations) still requires around twenty process steps per wiring layer. In this work, an approach to damascene processing that is based on step-and-flash imprint lithography (SFIL) is discussed. This imprint damascene process requires fewer than half as many steps as the standard photolithographic dual damascene approach. By using an imprint template with two levels of patterning, a single imprint lithography step can replace two photolithography steps. Further efficiencies are possible if the imprint resist material is itself a functional dielectric material. This work is a demonstration of the compatibility of imprint lithography (specifically SFIL) with back-end-of-line processing using a dual damascene approach with functional materials.