This paper describes a SEU fault injection framework. Based on the assumption of SEU effects and SEU distribution, the quantitative analysis between measured data and simulation model is investigated. By adjusting some parameters in the simulation-based framework, the proposed framework can be very possibly close to the published data and some accelerated radiation experiments. Furthermore, how the JPEG2000 based hardware architecture is sensitive to SEUs can be found out. In terms of hardware resources and operating frequencies, some fault-tolerant techniques can be introduced to the more sensitive parts, which show the framework's effectiveness in fault-tolerant design for image compression applications.
JPEG-LS is an ISO/ITU lossless/near-lossless compression standard for continuous-tone images with both low
complexity and good performance. However, the lack of rate control in JPEG-LS makes it unsuitable for applications,
which have the requirement of the compression to a pre-specified size for purpose of effective storage management or
effective bandwidth management. This paper proposes an efficient rate control scheme for JPEG-LS with a high bitrate.
It is based on a good relationship for the optimal quantization steps of different slices and a good relationship for the
optimal target bitrates of different slices. Comparing with the most previous JPEG-LS with rate control schemes, the
proposed rate control scheme has a uniform performance for the whole image, and it is more suited for the near-lossless
compression, but the most previous JPEG-LS with rate control schemes have the non-uniform performance. The
experimental results show that the proposed rate control scheme achieves better compression performance for remote
sensing compression with a high bitrate.
In this paper, we propose a lifting architecture based on a basic lifting unit, whose structure performs lifting
operations in a repetitive way. By analyzing computational processes in lifting in detail, the reusable Basic Lifting
Element (BLE) is presented. The BLE structure is designed and optimized from the viewpoint of hardware
implementation. The proposed lifting processor can be executed by arranging BLEs repeatedly. Experimental
results show that the proposed architecture can transform any size of tiles with 9/7 filter and 5/3 filter for lossy
and lossless compression, respectively. The lifting processor is designed in Verilog HDL and synthesized into
Xilinx FPGA, which can run up to 130MHz.