A novel hardware implementation of JPEG-LS Encoder based on FPGA is introduced in this paper. Using a look-ahead technique, the critical delay paths of LOCO-I algorithm, such as feedback-loop circuit of parameters updating, are improved. Then an optimized architecture of JPEG-LS Encoder is proposed. Especially, run-mode encode process of JPEG-LS is covered in the architecture as well. Experiment results show that the circuit complexity and memory consumption of the proposed structure are much lower, while the data processing speed is much higher than some other available structures. So it is very suited for applying high-speed lossless compression of satellite sensing image onboard.
This paper describes a SEU fault injection framework. Based on the assumption of SEU effects and SEU distribution, the quantitative analysis between measured data and simulation model is investigated. By adjusting some parameters in the simulation-based framework, the proposed framework can be very possibly close to the published data and some accelerated radiation experiments. Furthermore, how the JPEG2000 based hardware architecture is sensitive to SEUs can be found out. In terms of hardware resources and operating frequencies, some fault-tolerant techniques can be introduced to the more sensitive parts, which show the framework's effectiveness in fault-tolerant design for image compression applications.
We propose a zero block detection algorithm and architecture in EBCOT. After the
detailed analysis of wavelet coefficients’ precision and distribution in JPEG2000, there are three
main modes of zero coefficients in the wavelet domain, i.e. zero column, zero stripe and zero code
block. And we also discover that the coding information of each bit plane and the corresponding
passes can be obtained simultaneously in the hardware structure. Therefore, bit plane-parallel and
pass-parallel coding with zero detection is proposed, and its VLSI architecture is shown in details.
The analysis and the corresponding software/hardware experimental results show that the
proposed architecture reduces the processing time greatly compared with others.
An innovative VLSI architecture for JPEG-LS compression algorithm is proposed, which
implements real-time image compression either in near lossless mode or in lossless mode. The
proposed architecture mainly includes four parallel pipelines, in which four pixels from four
continuous lines could be processed simultaneously with a specific coding scan sequence, which
ensures low complexity and real-time data processing. Our VLSI architecture is implemented on a
Xilinx XC2VP30 FPGA. The experiment results show that our hardware system has the same results in
image quality and compression rate as the standard JPEG-LS method and the processing speed of our
system is four times more than that of traditional method.