The implementation of an effective readout integrated circuit for 320 x 256 middle-and long-wave infrared focal plane
arrays (MLIR FPAs) imaging system is detailed in this paper. The key purpose of this design is transferring the signals
from dual-color detectors sequentially with effectiveness including lower noise, less voltage loss, lower power
consumption, higher linearity, higher speed etc. A double sharing capacitor (DSC) structure is adopted as a solution to
how to make a trade-off between the areas of capacitors and the main MOSFETs structures. Compared to the traditional
charge transferring, a zero-charge-loss mechanism is applied in this circuit to guarantee a high voltage transferring
efficiency. A three-stage cascaded unit gain amplifiers is used to get a high drive capability and good linearity.
Meanwhile, a simple but effective power management is introduced to the section of arrays and the first output stage to
ensure acceptable power consumption. Moreover, a testing line with adjustable current source is added aside to fulfill the
effective testability. Now, the chip has been fabricated with the 0.35um 2P4M mixed signal technology and finished
basic testing process. According to the testing results, the whole chip presents a sensitive response to illumination and
the output voltage steps are clearly legible at 2.5MHz data transmission rate. As it is expected, this structure achieves
100f/s frame frequency and less than 1% nonlinearity under 5V power supply. However, the output swing reduced to 2V
at room temperature of which the reason should be researched further. The total power consumption reaches 170mW.
HgCdTe electron injection avalanche photodiodes (e-APDs) work at linear mode. A weak optical current signal is amplified orders of magnitude due to the internal avalanche mechanism and it has been demonstrated to be one of the most promising methods to focal-plane arrays (FPAs) for low-flux like hyper-spectral imaging and high-speed applications such as active imaging. This paper presents the design of a column-shared ADC for cooled e-APDs FPA. Designing a digital FPA requires fulfilling very stringent requirements in terms of power consumption, silicon area and speed. Among the various ADC architectures sigma-delta conversion is a promising solution for high-performance and medium size FPA such as 128×128. The performance of Sigma-delta ADC rather relies on the modulator structure which set over-