After model-based OPC and layer generation, the size of mask data is increasing beyond the limit that current software and hardware can handle. The file size of one of 512M DRAM mask data was 29 GB in GDSII and it could be reduced to 1.7 GB by transforming into OASIS. Compared to GDSII, OASIS included many effective features that could reduce the file size incredibly. In this paper, we adopted the repetitions in OASIS and used the concept to reduce the memory usage of mask data preparation software. We built a new data structure, called shape array that utilizes the repetition of mask data. Mask data is saved in OASIS and its repetition information is loaded onto memory. The data structure can be the basis for the mask data preparation operations such as region query, AND, XOR and so on. We implemented the region query in this paper. The region query is a major operation that a layout viewer uses. The mask data comparison operation, which is used to check the integrity of the mask data, is implemented with the shape array as well. The shape array method has used the memory of between 2 and 22 times less than the method that keeps the coordinate and attributes of each shape individually. The file loading time and the file writing time have improved 4~73 times and 1.5~14 times, respectively.
The global pattern density of a mask is a major factor of etch process-induced CD skew. Logic products have different global pattern densities according to the various area portions of SRAM and logic cells. For example, the pattern densities of 66 devices of 130nm node vary from 34% to 47.7% for active layer and from 14.7% to
26.7% for gate poly layer. In order to compensate the global pattern density effect on CD skew, the process condition change is easy to practice for process engineers. But the process condition change for each device increases process variation and reduces process margin. A direct approach to compensate the global density effect on CD skew is necessary.
In this paper, we propose a method to make the global pattern density of a mask uniform at the data preparation stage. Our approach is to resize fill patterns to control the global pattern density. We confirmed that the proposed method is effective to control the global pattern densities of masks to a target density within +/- 1%.
The lithography verification of critical dimension variation, pinching, and bridging becomes indispensable in synthesizing mask data for the photolithography process. In handling IC layout data, the software usually use the hierarchical information of the design to reduce execution time and to overcome peak memory usage. However, the layout data become flattened by resolution enhancement techniques, such as optical proximity correction, assist features insertion, and dummy pattern insertion. Consequently, the lithography verification software should take burden of processing the flattened data.
This paper describes the hierarchy restructuring and artificial neural networks methods in developing a rapid lithography verification system. The hierarchy restructuring method is applied on layout patterns so that the lithography verification on the flattened layout data can attain the speed of hierarchical processing. Artificial neural networks are employed to replace lithography simulation. We define input parameters, which is major factors in determining patterns width, for the artificial neural network system. We also introduce a learning technique in the neural networks to achieve accuracy comparable to an existing lithography verification system. Failure detection with artificial neural networks outperforms the methods that use the convolution-based simulation. The proposed system shows 10 times better performance than a widely accepted system while it achieves the same predictability on lithography failures.