There are strong demands for techniques which are able to extend application of ArF immersion lithography.
Especially, the leading edge techniques are required to make very small hole patterns below 50nm. Several
techniques such as double patterning technique, free-form illumination and resist shrinkage technology are
considered as viable candidates. Most of all, NTD (Negative Tone Development) is being regarded as the most
promising technology for the realization of small hole patterns
When NTD process is applied, hole patterns are defined by island type features on the reticle and consequently its
optical performance shows better result compared with PTD (Positive Tone Development) process. However it is
still difficult to define extremely small hole patterns below 40nm, new combination process of NTD with RELACS
is being introduced to overcome resolution limitation. NTD combined with RELACS, which is the most advanced
lithography technology, definitely enable us to generate smaller size hole patterns on the wafer.
A chemical shrinkage technology, RELACS (Resolution Enhancement Lithography Assisted by Chemical Shrink),
utilizes the cross linking reaction catalyzed by the acid component existing in a predefined resist pattern. In case of
PTD combined with RELACS process, we already know that CD change after the shrinkage process is not
influenced by duty ratio. So we could easily reflect the RELACS bias to meet the CD target during OPC (Optical
Proximity Correction) procedure.
But NTD combined with RELACS process was not understood clearly, nor verified. It requires more investigation
of physical behavior during combined process in order to define exact hole patterns. The newly introduced process
might require additive OPC modeling procedure to satisfy target CD when NTD RELACS bias has different values
according to pitch and shape.
This study is going to include the investigation on two types of resist shrinkage process, PTD and NTD. The
optimized OPC methodology will be discussed through the evaluation on simple array hole patterns and random
As K1 factor for mass-production of memory devices has been decreased to almost its theoretical limit, the process
window of lithography is getting much smaller and the production yield has become more sensitive to even small
variations of the process in lithography. So it is necessary to control the process variations more tightly than ever. In
mass-production, it is very hard to extend the production capacity if the tool-to-tool variation of scanners and/or scanner
stability through time is not minimized. One of the most critical sources of variation is the illumination pupil. So it is
critical to qualify the shape of pupils in scanners to control tool-to-tool variations.
Traditionally, the pupil shape has been analyzed by using classical pupil parameters to define pupil shape, but these
basic parameters, sometimes, cannot distinguish the tool-to-tool variations. It has been found that the pupil shape can be
changed by illumination misalignment or damages in optics and theses changes can have a great effect on critical
dimension (CD), pattern profile or OPC accuracy. These imaging effects are not captured by the basic pupil parameters.
The correlation between CD and pupil parameters will become even more difficult with the introduction of more
complex (freeform) illumination pupils.
In this paper, illumination pupils were analyzed using a more sophisticated parametric pupil description (Pupil Fit
Model, PFM). And the impact of pupil shape variations on CD for critical features is investigated. The tool-to-tool
mismatching in gate layer of 4X memory device was demonstrated for an example. Also, we interpreted which
parameter is most sensitive to CD for different applications. It was found that the more sophisticated parametric pupil
description is much better compared to the traditional way of pupil control. However, our examples also show that the
tool-to-tool pupil variation and pupil variation through time of a scanner can not be adequately monitored by pupil
parameters only, The best pupil control strategy is a combination of pupil parameters and simulated CD using measured
illumination pupils or modeled pupils.
During the past few years, new technology brought about new problems we face today due to
shrinkage of the feature size. Some of the problems such as Mask Error Enhancement Factor (MEEF), overlay
control, and so on are crucial because large MEEF can make it difficult to satisfy CD target, and bring about
large CD variation. Moreover, it can also lead to degraded CD uniformity which would have an undesired
influence on device properties. Recently, 2-D random contact hole is getting crucial because it normally has
very large MEEF and cause asymmetric proximity effect which can cause large CD variation, and
misalignment of layer-to-layer. In other words, the method of optical proximity correction and building
accurate OPC model for 2-D random contact hole pattern could be key factor obtaining better CD uniformity
with enhanced overlay margin. Furthermore, in order to get very tangible performance, design based
metrology system (DBM) is used to evaluate process performance. Design based metrology systems are able
to extract information of whole chip CD variation. On top of that, OPC abnormality can be identified and
design feedback can be also disclosed.
In this paper, we will investigate novel method for sub 45nm 2-D random contact hole printing.
First, optical proximity effect (OPE) for two dimensional layout will be investigated. Second, the results of
Variable Threshold Modeling (VTM) for various slit contact hole patterns will be analyzed. Third, model
based verification will be done and analyzed through full-chip before creating full-chip mask. Finally, sub
45nm 2-D random contact hole printing performance will be presented by DBM.
In resolution limited lithography process, the contact hole pattern is one of the most challenging features to be printed on wafer. A lot of lithographers struggle to make robust hole patterns under 45nm node, especially if the contact hole patterns are composed of dense array and isolated hole simultaneously. The strong OAI(Off Axis Illumination) such as dipole is very useful technique to enhance resolution for specific features. However the contact hole formed by dipole illumination usually has elliptical shape and the asymmetric feature leads to increment of chip size.
In this paper, we will explore the lithographic feasibility for the coexisting dense array with isolated contact holes and the technical issues are investigated to generate finer contact hole for both dense and isolated feature. Conventional illumination with resist shrinkage technique will be used to generate dense array and isolated contact hole maintaining original shape for the sub-50nm node memory device.
Recently, the dramatic acceleration in dimensional shrink of DRAM memory devices has been observed. For sub 60 nm memory device, we suggest the following method of optical proximity correction (OPC) to enhance the critical dimension uniformity (CDU). In order to enhance CD variation of each transistor, hundreds of thousand transistor CD data were used through design based metrology (DBM) system. In a traditional OPC modeling method, it is difficult to realize enhancement of CD variation on chip because of the limitation of OPC feedback data.
Even though optical properties are surely understood from recent computational lithography models, there are so many abnormalities like mask effect, thermal effect from the wafer process, and etch bias variation of the etching process. Especially, etch bias is too complicate to predict since it is related to variations such as space among adjacent patterns, the density of neighboring patterns and so on.
In this paper, process proximity correction (PPC) adopting the pattern to pattern matching method is used with huge amount of CD data from real wafer. This is the method which corrects CD bias with respect to each pattern by matching the same coordinates. New PPC method for enhancement of full chip CD variation is proposed which automatically corrects off-targeted feature by using full chip CD measurement data of DBM system. Thus, gate CDU of sub 60 nm node is reduced by using new PPC method. Analysis showed that our novel PPC method enhanced CD variation of full chip up to 20 percent.
New concepts about transistor structure are being introduced for sub-50nm memory products. As the memory cell
design is shrinking down, conventional transistor of planar structure can not guarantee safe transistor operation.
Newly introduced transistor has to ensure robust transistor operation characteristics and process stability
simultaneously. One of the candidates which are being developed recently is vertical transistor. The basic layout to
integrate vertical transistor include very dense 2-dimensional features. The new memory cell based on dense structure
can also contribute to reduction of cell area compared to conventional memory cell such as 8F2 planar cell. While new
memory structure enables the reduction of chip size, its 2-dimensional structure limits resolving performance of optical
lithography inevitably. It is very challenging to build 4F2 dense features of sub-50nm node by single exposure
technology using hyper NA ArF lithography before the EUV era. In this paper, the feasibility of 2-dimensional dense
structure at 50nm node is presented and various techniques are introduced to realize new memory scheme as next
generation memory cell structure.