Dr. Byung Jin Choi Profile

Dr. Byung Jin Choi

Sr VP of Advanced Engineering at Canon Nanotechnologies Inc

SPIE Involvement:

Author

Publications (30)

Proceedings Article | 1 December 2022 Presentation + Paper

Presentation + Paper

Nanoimprint performance improvements for high volume semiconductor device manufacturing

Toshihiro Ifuku, Mitsuru Hiura, Yukio Takabayashi, Atsushi Kimura, Yoshio Suzaki, Toshiki Ito, Kiyohito Yamamoto, Byung Jin Choi, Teresa Estrada, Douglas Resnick

Proceedings Volume 12293, 122930E (2022) https://doi.org/10.1117/12.2643212

KEYWORDS: Nanoimprint lithography, Photomasks, Semiconducting wafers, Overlay metrology, Particles, Semiconductors, Optical lithography, Distortion, Logic

Read Abstract +

Imprint lithography is an effective and well-known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. Memory fabrication is challenging, in particular for DRAM, because the roadmap for DRAM calls for continued scaling, eventually reaching half pitches of 14nm and beyond. For DRAM, overlay on some critical layers is much tighter than NAND Flash, with an error budget of 15-20% of the minimum half pitch. For 14nm, this means 2.1-2.8nm. DRAM device design is also challenging, and layouts are not always conducive to pitch dividing methods such as SADP and SAQP. This makes a direct printing process, such as NIL an attractive solution. Logic is more challenging from a defectivity perspective, often requiring defect levels significantly lower than memory devices that incorporate redundancy. In this paper, we touch on the markets that can be addressed with NIL and also describe the efforts to further improve NIL performance. We specifically focus on performance improvements related to overlay and defectivity. For overlay, we present results on stability and also discuss new methods to further address high order distortion. For defectivity, we review random defect generation, particle adders and mask inspection methods. In addition, we also discuss Canon’s recent involvement in the New Energy and Industrial Technology Development Organization (NEDO) project and its goals related to logic devices. As a final topic, we describe Canon’s interests in fabrication beyond traditional advanced semiconductor devices.

Proceedings Article | 25 May 2022 Presentation + Paper

Presentation + Paper

Nanoimprint lithography: today and tomorrow

Hirotoshi Torii, Mitsuru Hiura, Yukio Takabayashi, Atsushi Kimura, Yoshio Suzaki, Toshiki Ito, Kiyohito Yamamoto, Byung Jin Choi, Teresa Estrada

Proceedings Volume 12054, 1205403 (2022) https://doi.org/10.1117/12.2615740

KEYWORDS: Nanoimprint lithography, Photomasks, Etching, Optical lithography, Semiconducting wafers, Molybdenum, Logic, Helium, Semiconductors, Overlay metrology

Read Abstract +

Imprint lithography is an effective and well-known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. In this review paper, we touch on the markets that can be addressed with NIL and also describe the efforts to further improve NIL performance. In addition, we describe recent efforts to develop pattern transfer processes that can be used to address edge placement error. As a final topic, we describe Canon’s efforts in developing a sustainable future and touch on how new methods can be applied to reduce waste and enable environmentally friendly solutions.

SPIE Journal Paper | 4 January 2022

Overlay models for nanoimprint lithography

Nilabh Roy, Mario Meissl, Takahiro Yoshida, Anshuman Cherala, Xiaoming Lu, Jeff Klein, Mingji Lou, Jin Choi, Hiroyuki Sekiguchi, Takashi Shibayama, Mitsuru Hiura

JM3, Vol. 21, Issue 01, 011004, (January 2022) https://doi.org/10.1117/12.10.1117/1.JMM.21.1.011004

KEYWORDS: Semiconducting wafers, Nanoimprint lithography, Overlay metrology, Head, Actuators, Calibration, Distortion, Photomasks, Optical lithography, Error analysis

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Proceedings Article | 12 October 2021 Presentation + Paper

Presentation + Paper

Nanoimprint lithography methods for achieving sub-3nm overlay

Kenji Yamamoto, Hideyuki Wada, Yoshio Suzaki, Kazuhiro Sato, Satoshi Iino, Satoru Jimbo, Osamu Morimoto, Mitsuru Hiura, Nilabh Roy, Anshuman Cherala, Jin Choi

Proceedings Volume 11855, 1185509 (2021) https://doi.org/10.1117/12.2601937

KEYWORDS: Distortion, Photomasks, Nanoimprint lithography, Semiconducting wafers, Overlay metrology

Read Abstract +

Imprint lithography is an effective and well-known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field/shot-by-field/shot deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. Any new lithographic technology to be introduced into manufacturing must deliver either a performance advantage or a cost advantage. Key technical attributes include alignment, overlay, defectivity and throughput. Advanced memories, such as DRAM and phase change memory are challenging, because the roadmap for these devices calls for continued scaling, eventually reaching half pitches of 14nm and beyond. Scaling also impacts the overlay budget. For DRAM, as an example, overlay on some critical layers is much tighter than NAND Flash, with an error budget of 15-20% of the minimum half pitch. For 14nm, this means 2.1nm - 2.8nm. DRAM device design is also challenging, and layouts are not always conducive to pitch dividing methods such as self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP). This makes a direct printing process, such as NIL an attractive solution. In previous papers, overlay has been addressed by applying methods that are unique to NIL. In 2018, Hiura et al. reported a mix and match overlay (MMO) of 3.4 nm and a single machine overlay (SMO) across the wafer was 2.5nm using an FPA-1200 NZ2C four station cluster tool. These results were achieved by combining a magnification actuator system with a High Order Distortion Correction (HODC) system, thereby enabling correction of high order distortion terms up to K30. The HODC system utilizes a digital micro mirror array to correct distortion on a field-by-field basis. Further improvements to the system have been achieved by extending the range of the HODC system by applying a diamond like carbon film to the wafer chuck in order to reduce friction. Other process variables that are unique to NIL and that can be considered as process tunable variables include imprint force and tip/tilt of the imprint head relative to the wafer substrate during exposure. These variables can be used to modulate and control the overlay errors near the imprint field edges and provide good overlay control. An additional method to improve overlay is Drop Pattern Compensation (DPC). DPC is used to create a resist drop pattern designed to remove non-flatness originating either from the wafer/wafer chuck or pattern topography, so as to minimize mask bending. Finally, it is also possible to correct distortion signatures on wafer by fabricating a “refined” mask which takes into account the distortion signature. The purpose of this paper is to describe the application of the improvements discussed above to realize a mix and match overlay of less than 3nm.

Proceedings Article | 9 March 2021 Presentation + Paper

Presentation + Paper

Nanoimprint performance improvements for high volume semiconductor device manufacturing

Mitsuru Hiura, Yukio Takabayashi, Atsushi Kimura, Hiroshi Morohoshi, Yoshio Suzaki, Takahiro Matsumoto, Anshuman Cherala, Jin Choi

Proceedings Volume 11610, 1161005 (2021) https://doi.org/10.1117/12.2584675

KEYWORDS: Optical alignment, Semiconducting wafers, Nanoimprint lithography, Photomasks, Overlay metrology, Manufacturing, Semiconductors, Semiconductor manufacturing, Particles, Optical lithography

Read Abstract +

Imprint lithography is an effective and well-known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. DRAM memory is challenging, because the roadmap for DRAM calls for continued scaling, eventually reaching half pitches of 14nm and beyond. For DRAM, overlay on some critical layers is much tighter than NAND Flash, with an error budget of 15-20% of the minimum half pitch. For 14nm, this means 2.1-2.8nm. DRAM device design is also challenging, and layouts are not always conducive to pitch dividing methods such as SADP and SAQP. This makes a direct printing process, such as NIL and attractive solution. The purpose of this paper is to review the performance improvements related to overlay, resolution and pattern transfer. Improvements in overlay include control methods such as imprint force, mask to wafer tip/tilt and pneumatic controls at the wafer edge. We also introduce the pattern transfer scheme used to etch features with half pitches below 20nm.

Proceedings Article | 1 March 2021 Presentation + Paper

Presentation + Paper

Overlay models for nanoimprint lithography

Nilabh Roy, Mario Meissl, Takahiro Yoshida, Anshuman Cherala, Xiaoming Lu, Jeffrey Klein, Mingji Lou, Jin Choi, Hiroyuki Sekiguchi, Takashi Shibayama, Mitsuru Hiura

Proceedings Volume 11610, 1161006 (2021) https://doi.org/10.1117/12.2584742

KEYWORDS: Nanoimprint lithography, Overlay metrology, Optical alignment, Semiconducting wafers, Photomasks, Wafer testing, Optical lithography, Ultraviolet radiation, Signal processing, Lithography

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Proceedings Article | 23 March 2020 Paper

Paper

Addressing nanoimprint lithography mix and match overlay using drop pattern compensation

Anshuman Cherala, Se-Hyuk Im, Mario Meissl, Logan Simpson, Ecron Thompson, Jin Choi, Mitsura Hiura, Satoshi Iino

Proceedings Volume 11324, 113240C (2020) https://doi.org/10.1117/12.2552023

KEYWORDS: Distortion, Photomasks, Semiconducting wafers, Nanoimprint lithography, Optical alignment, Ultraviolet radiation, Overlay metrology, Wafer testing, Semiconductors

Read Abstract +

Imprint lithography is a promising technology for replication of nano-scale features. For semiconductor device applications, Canon deposits a low viscosity resist on a field by field basis using jetting technology. A patterned mask is lowered into the resist fluid, which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. Overlay budgets play a large role in defining production readiness. As an example, DRAM devices require overlay on the order of 15-20% of the half pitch. Canon uses a through the mask (TTM) alignment system to measure a Moiré image anywhere in the field. This system can also record alignment errors of all fields and all marks. The data collected by the TTM system correlates very closely with an Archer measurement tool. In addition, a High Order Distortion Correction (HODC) system, which applies a heat input on a field by field basis through the use of a DMD array has been combined with magnification actuators to correct high order distortion terms up to K30. There is an additional distortion term that must also be addressed for the case of nanoimprint lithography. NIL drop patterns are typically designed to minimize resist fill time and create a uniform residual layer beneath the resist pattern. For device wafers, however, it is important to recognize that there are both long wavelength flatness errors coming from the wafer chuck and existing pattern topography from previously patterned levels that cause out of plane errors. When the mask comes in contact with the resist on the wafer, these out of plane errors can then induce mask bending, resulting in an additional distortion term. To minimize this distortion, a Drop Pattern Compensation (DPC) Model has been implemented to minimize the added distortion terms. In this paper we present an updated study and report on nanoimprint mix and match overlay improvements using DPC. In addition, we describe how the mode array and peak to valley thickness of the resist impacts distortion correction.

Proceedings Article | 26 September 2019 Presentation + Paper

Presentation + Paper

Patterning, mask life, throughput and overlay improvements for high volume semiconductor manufacturing using nanoimprint lithography

Osamu Morimoto, Takehiko Iwanaga, Yukio Takabayashi, Keita Sakai, Wei Zhang, Anshuman Cherala, Se-Hyuk Im, Mario Meissl, Jin Choi

Proceedings Volume 11148, 111480M (2019) https://doi.org/10.1117/12.2535912

KEYWORDS: Photomasks, Optical lithography, Nanoimprint lithography, Stochastic processes, Semiconductor manufacturing, Particles, Semiconducting wafers, Lithography, Manufacturing equipment, Capillaries

Read Abstract +

Imprint lithography is an effective and well-known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. Any new lithographic technology to be introduced into manufacturing must deliver either a performance advantage or a cost advantage. Key technical attributes include alignment, overlay and throughput. In previous papers, overlay and throughput results have been reported on test wafers. In this work, we review progress on pattern capability, throughput, mask life and overlay. To minimize distortion and improve overlay, a Drop Pattern Compensation (DPC) method has been implemented to minimize the added overlay distortion terms. In this paper we describe the origins of the out of plane errors, and describe the method used to correct these errors along with some examples. Improvements to both cross matched machine overlay (XMMO) and imprint mix and match overlay (IMMO) are presented.

Proceedings Article | 16 May 2019 Paper

Paper

Topography and flatness induced overlay distortion correction using resist drop pattern compensation in nanoimprint lithography systems

Anshuman Cherala, Se-Hyuk Im, Mario Meissl, Ahmed Hussein, Logan Simpson, Ryan Minter, Ecron Thompson, Jin Choi, Mitsuru Hiura, Satoshi Iino

Proceedings Volume 10958, 109580C (2019) https://doi.org/10.1117/12.2515146

KEYWORDS: Photomasks, Semiconducting wafers, Distortion, Nanoimprint lithography, Overlay metrology, Optical alignment, Ultraviolet radiation, Data modeling, Semiconductors, Capillaries

Read Abstract +

Imprint lithography is a promising technology for replication of nano-scale features. For semiconductor device applications, Canon deposits a low viscosity resist on a field by field basis using jetting technology. A patterned mask is lowered into the resist fluid, which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. Overlay budgets play a large role in defining production readiness. As an example, DRAM devices require overlay on the order of 20% of the half pitch. Canon uses a through the mask (TTM) alignment system to measure a Moiré image anywhere in the field. This system can also record alignment errors of all fields and all marks. The data collected by the TTM system correlates very closely with an Archer measurement tool. In addition, a High Order Distortion Correction (HODC) system, which applies a heat input on a field by field basis through the use of a DMD array has been combined with magnification actuators to correct high order distortion terms up to K30. There is an additional distortion term that must also be addressed for the case of nanoimprint lithography. NIL drop patterns are typically designed to minimize resist fill time and create a uniform residual layer beneath the resist pattern. For device wafers, however, it is important to recognize that there are both long wavelength flatness errors coming from the wafer chuck and existing pattern topography from previously patterned levels that cause out of plane errors. When the mask comes in contact with the resist on the wafer, these out of plane errors can then induce mask bending, resulting in an additional distortion term. To minimize this distortion, a Drop Pattern Compensation (DPC) Model has been implemented to minimize the added distortion terms. In this paper we describe the origins of the out of plane errors, and describe the model used to correct these errors along with some examples. Finally, results are presented for a device like wafer in which the overlay errors within a field are reduced from 5.4nm to 3.4nm, 3 sigma.

Proceedings Article | 3 October 2018 Paper

Paper

High volume semiconductor manufacturing using nanoimprint lithography

Zenichi Hamaya, Junichi Seki, Toshiya Asano, Keita Sakai, Ali Aghili, Makoto Mizuno, Jin Choi, Chris Jones

Proceedings Volume 10810, 108100F (2018) https://doi.org/10.1117/12.2501008

KEYWORDS: Photomasks, Particles, Semiconducting wafers, Nanoimprint lithography, Mask cleaning, Polishing, Overlay metrology, Control systems, Surface finishing, Optical lithography

Read Abstract +

Proceedings Article | 19 March 2018 Paper

Paper

Performance of a nanoimprint mask replication system

Atsushi Kimura, Kohei Imoto, Chiaki Sato, Kiyohito Yamamoto, Hiroshi Inada, Mitsuru Hiura, Takehiko Iwanaga, Ali Aghili, Makoto Mizuno, Jin Choi, Chris Jones

Proceedings Volume 10584, 105840Q (2018) https://doi.org/10.1117/12.2299636

KEYWORDS: Photomasks, Particles, Semiconducting wafers, Nanoimprint lithography, Optical lithography, Mask cleaning, Lithography, Manufacturing equipment, Capillaries, Ultraviolet radiation

Read Abstract +

Proceedings Article | 16 October 2017 Paper

Paper

Progress in nanoimprint wafer and mask systems for high volume semiconductor manufacturing

Kohei Imoto, Mitsuru Hiura, Hiroshi Morohoshi, Tatsuya Hayashi, Atsushi Kimura, Yoshio Suzaki, Jin Choi

Proceedings Volume 10451, 104511B (2017) https://doi.org/10.1117/12.2280440

KEYWORDS: Photomasks, Semiconducting wafers, Lithography, Overlay metrology, Nanoimprint lithography, Particles, Semiconductors, Distortion, Semiconductor manufacturing, Capillaries

Read Abstract +

Proceedings Article | 13 July 2017 Paper

Paper

Improved particle control for high volume semiconductor manufacturing for nanoimprint lithography

Masami Yonekawa, Takahiro Nakayama, Kazuki Nakagawa, Toshihiro Maeda, Yoichi Matsuoka, Keiji Emoto, Hisanobu Azuma, Yukio Takabayashi, Ali Aghili, Makoto Mizuno, Jin Choi, Chris Jones

Proceedings Volume 10454, 104540R (2017) https://doi.org/10.1117/12.2279365

KEYWORDS: Semiconducting wafers, Curtains, Polishing, Lithography, Liquids, Ceramics, Nanoimprint lithography, Particles, Control systems, Semiconductor manufacturing, Photomasks

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Proceedings Article | 21 March 2017 Paper

Paper

Improved defectivity and particle control for nanoimprint lithography high-volume semiconductor manufacturing

Takahiro Nakayama, Masami Yonekawa, Yoichi Matsuoka, Hisanobu Azuma, Yukio Takabayashi, Ali Aghili, Makoto Mizuno, Jin Choi, Chris Jones

Proceedings Volume 10144, 1014407 (2017) https://doi.org/10.1117/12.2257647

KEYWORDS: Photomasks, Particles, Nanoimprint lithography, Lithography, Semiconductors, Control systems, Semiconductor manufacturing, Ultraviolet radiation, Optical lithography, Semiconducting wafers, Curtains, Ceramics, Surface finishing, Polishing

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Proceedings Article | 21 March 2017 Presentation + Paper

Presentation + Paper

Nanoimprint system development for high-volume semiconductor manufacturing the and status of overlay performance

Yukio Takabayashi, Mitsuru Hiura, Hiroshi Morohoshi, Nobuhiro Kodachi, Tatsuya Hayashi, Atsushi Kimura, Takahiro Yoshida, Kazuhiko Mishima, Yoshio Suzaki, Jin Choi

Proceedings Volume 10144, 1014405 (2017) https://doi.org/10.1117/12.2258385

KEYWORDS: Photomasks, Nanoimprint lithography, Semiconducting wafers, Optical alignment, Distortion, Overlay metrology, Semiconductor manufacturing, Lithography, Semiconductors, Particles, Actuators, Source mask optimization

Read Abstract +

Proceedings Article | 20 October 2016 Paper

Paper

Nanoimprint system development and status for high volume semiconductor manufacturing

Hiromi Hiura, Yukio Takabayashi, Tsuneo Takashima, Keiji Emoto, Jin Choi, Phil Schumaker

Proceedings Volume 10032, 100320E (2016) https://doi.org/10.1117/12.2248363

KEYWORDS: Nanoimprint lithography, Overlay metrology, Particles, Photomasks, Semiconducting wafers, Curtains, Lithography, Semiconductors, Actuators, Data modeling

Read Abstract +

Imprint lithography has been shown to be an effective technique for replication of nano-scale features. Jet and Flash Imprint Lithography* (J-FIL*) involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. There are many criteria that determine whether a particular technology is ready for wafer manufacturing. For imprint lithography, recent attention has been given to the areas of overlay, throughput, defectivity, and mask replication. This paper reviews progress in these critical areas. Recent demonstrations have proven that mix and match overlay of less than 5nm can achieved. Further reductions require a higher order correction system. Modeling and experimental data are presented which provide a path towards reducing the overlay errors to less than 3nm. Throughput is mainly impacted by the fill time of the relief images on the mask. Improvement in resist materials provides a solution that allows 15 wafers per hour per station, or a tool throughput of 60 wafers per hour. Defectivity and mask life play a significant role relative to meeting the cost of ownership (CoO) requirements in the production of semiconductor devices. Hard particles on a wafer or mask create the possibility of inducing a permanent defect on the mask that can impact device yield and mask life. By using material methods to reduce particle shedding and by introducing an air curtain system, the lifetime of both the master mask and the replica mask can be extended. In this work, we report results that demonstrate a path towards achieving mask lifetimes of better than 1000 wafers. Finally, on the mask side, a new replication tool, the FPA-1100NR2 is introduced. Mask replication is required for nanoimprint lithography (NIL), and criteria that are crucial to the success of a replication platform include both particle control and IP accuracy. In particular, by improving the specifications on the mask chuck, residual errors of only 1nm can be realized.

Proceedings Article | 4 October 2016 Paper

Paper

Nanoimprint wafer and mask tool progress and status for high volume semiconductor manufacturing

Yoichi Matsuoka, Junichi Seki, Takahiro Nakayama, Kazuki Nakagawa, Hisanobu Azuma, Kiyohito Yamamoto, Chiaki Sato, Fumio Sakai, Yukio Takabayashi, Ali Aghili, Makoto Mizuno, Jin Choi, Chris Jones

Proceedings Volume 9985, 99851G (2016) https://doi.org/10.1117/12.2243114

KEYWORDS: Photomasks, Lithography, Nanoimprint lithography, Semiconducting wafers, Semiconductors, Particles, Semiconductor manufacturing, Curtains, Image resolution, Manufacturing

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Proceedings Article | 22 March 2016 Paper

Paper

Nanoimprint system development and status for high-volume semiconductor manufacturing

Tsuneo Takashima, Yukio Takabayashi, Naosuke Nishimura, Keiji Emoto, Takahiro Matsumoto, Tatsuya Hayashi, Atsushi Kimura, Jin Choi, Philip Schumaker

Proceedings Volume 9777, 977706 (2016) https://doi.org/10.1117/12.2219001

KEYWORDS: Photomasks, Nanoimprint lithography, Lithography, Overlay metrology, Semiconductor manufacturing, Semiconductors, Semiconducting wafers, Particles, Capillaries, Ultraviolet radiation, Distortion, High volume manufacturing, Actuators

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Proceedings Article | 22 March 2016 Paper

Paper

Defectivity and particle reduction for mask life extension, and imprint mask replication for high-volume semiconductor manufacturing

Keiji Emoto, Fumio Sakai, Chiaki Sato, Yukio Takabayashi, Hitoshi Nakano, Tsuneo Takabayashi, Kiyohito Yamamoto, Tadashi Hattori, Mitsuru Hiura, Toshiaki Ando, Yoshio Kawanobe, Hisanobu Azuma, Takehiko Iwanaga, Jin Choi, Ali Aghili, Chris Jones, J. W. Irving, Brian Fletcher, Zhengmao Ye

Proceedings Volume 9777, 97770C (2016) https://doi.org/10.1117/12.2219036

KEYWORDS: Photomasks, Particles, Nanoimprint lithography, Lithography, Semiconductors, Control systems, Semiconductor manufacturing, Ultraviolet radiation, Optical lithography, Dry etching, Semiconducting wafers, Curtains, Liquids, Ceramics, Overlay metrology

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Proceedings Article | 28 March 2014 Paper

Paper

High volume nanoscale roll-based imprinting using jet and flash imprint lithography

Se Hyun Ahn, Michael Miller, Shuqiang Yang, Maha Ganapathisubramanian, Marlon Menezes, Vik Singh, Fen Wan, Jin Choi, Frank Xu, Dwayne LaBrake, Douglas Resnick, Paul Hofemann, S. Sreenivasan

Proceedings Volume 9049, 90490G (2014) https://doi.org/10.1117/12.2048172

KEYWORDS: Lithography, Polarizers, LCDs, Optical lithography, Aluminum, Etching, Transmittance, Nanostructures, Electron beam lithography, Organic light emitting diodes

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Proceedings Article | 26 September 2013 Paper

Paper

High volume nanoscale roll-based imprinting using jet and flash imprint lithography

Se Hyun Ahn, Mike Miller, Shuqiang Yang, Maha Ganapathisubramanian, Marlon Menezes, Vik Singh, Jin Choi, Frank Xu, Dwayne LaBrake, Douglas Resnick, S. V. Sreenivasan

Proceedings Volume 8816, 881602 (2013) https://doi.org/10.1117/12.2027765

KEYWORDS: Aluminum, Polarizers, Lithography, Ions, Etching, Transmission electron microscopy, Manufacturing, Nanostructures, Glasses, Opacity

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Proceedings Article | 26 March 2013 Paper

Paper

High performance wire grid polarizers using jet and flashTM imprint lithography

Sean Ahn, Jack Yang, Mike Miller, Maha Ganapathisubramanian, Marlon Menezes, Jin Choi, Frank Xu, Douglas Resnick, S. V. Sreenivasan

Proceedings Volume 8680, 86800W (2013) https://doi.org/10.1117/12.2013692

KEYWORDS: Polarizers, Lithography, Aluminum, Nanoimprint lithography, Etching, Nanostructures, Opacity, Ultraviolet radiation, Neodymium, Manufacturing

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The ability to pattern materials at the nanoscale can enable a variety of applications ranging from high density data storage, displays, photonic devices and CMOS integrated circuits to emerging applications in the biomedical and energy sectors. These applications require varying levels of pattern control, short and long range order, and have varying cost tolerances. Extremely large area roll to roll (R2R) manufacturing on flexible substrates is ubiquitous for applications such as paper and plastic processing. It combines the benefits of high speed and inexpensive substrates to deliver a commodity product at low cost. The challenge is to extend this approach to the realm of nanopatterning and realize similar benefits. The cost of manufacturing is typically driven by speed (or throughput), tool complexity, cost of consumables (materials used, mold or master cost, etc.), substrate cost, and the downstream processing required (annealing, deposition, etching, etc.). In order to achieve low cost nanopatterning, it is imperative to move towards high speed imprinting, less complex tools, near zero waste of consumables and low cost substrates. The Jet and Flash Imprint Lithography (J-FIL^TM) process uses drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for memory markets including Flash memory and patterned media for hard disk drives. In this paper we have developed a roll based J-FIL process and applied it to technology demonstrator tool, the LithoFlex 100, to fabricate large area flexible bilayer wire grid polarizers (WGP) and high performance WGPs on rigid glass substrates. Extinction ratios of better than 10000 were obtained for the glass-based WGPs. Two simulation packages were also employed to understand the effects of pitch, aluminum thickness and pattern defectivity on the optical performance of the WGP devices. It was determined that the WGPs can be influenced by both clear and opaque defects in the gratings, however the defect densities are relaxed relative to the requirements of a high density semiconductor device.

Proceedings Article | 21 March 2012 Paper

Paper

Roll-to-roll nanopatterning using jet and flash imprint lithography

Sean Ahn, Maha Ganapathisubramanian, Mike Miller, Jack Yang, Jin Choi, Frank Xu, Douglas Resnick, S. Sreenivasan

Proceedings Volume 8323, 83231L (2012) https://doi.org/10.1117/12.918040

KEYWORDS: Nanostructures, Lithography, Etching, Manufacturing, Optical lithography, Polarizers, Ultraviolet radiation, Data storage, Photonic devices, Integrated circuits

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The ability to pattern materials at the nanoscale can enable a variety of applications ranging from high density data storage, displays, photonic devices and CMOS integrated circuits to emerging applications in the biomedical and energy sectors. These applications require varying levels of pattern control, short and long range order, and have varying cost tolerances. Extremely large area R2R manufacturing on flexible substrates is ubiquitous for applications such as paper and plastic processing. It combines the benefits of high speed and inexpensive substrates to deliver a commodity product at low cost. The challenge is to extend this approach to the realm of nanopatterning and realize similar benefits. The cost of manufacturing is typically driven by speed (or throughput), tool complexity, cost of consumables (materials used, mold or master cost, etc.), substrate cost, and the downstream processing required (annealing, deposition, etching, etc.). In order to achieve low cost nanopatterning, it is imperative to move towards high speed imprinting, less complex tools, near zero waste of consumables and low cost substrates. The Jet and Flash Imprint Lithography (J-FIL^TM) process uses drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for memory markets including Flash memory and patterned media for hard disk drives. In this paper we address the key challenges for roll based nanopatterning by introducing a novel concept: Ink Jet based Roll-to-Roll Nanopatterning. To address this challenge, we have introduced a J-FIL based demonstrator product, the LithoFlex 100. Topics that are discussed in the paper include tool design and process performance. In addition, we have used the LithoFlex 100 to fabricate high performance wire grid polarizers on flexible polycarbonate (PC) films. Transmission of better than 80% and extinction ratios on the order of 4500 have been achieved.

Proceedings Article | 20 May 2004 Paper

Paper

Development of imprint materials for the Step and Flash Imprint Lithography process

Frank Xu, Nicholas Stacey, Mike Watts, Van Truskett, Ian McMackin, Jin Choi, Philip Schumaker, Ecron Thompson, Daniel Babbs, S. Sreenivasan, C. Grant Willson, Norman Schumaker

Proceedings Volume 5374, (2004) https://doi.org/10.1117/12.538734

KEYWORDS: Lithography, Ultraviolet radiation, Silicon, Optical lithography, Liquids, Semiconducting wafers, Etching, Optical alignment, Scanning electron microscopy, Interfaces

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Proceedings Article | 20 May 2004 Paper

Paper

Step and Repeat UV nanoimprint lithography tools and processes

Ian McMackin, Jin Choi, Philip Schumaker, Van Nguyen, Frank Xu, Ecron Thompson, Daniel Babbs, S. Sreenivasan, Mike Watts, Norman Schumaker

Proceedings Volume 5374, (2004) https://doi.org/10.1117/12.538733

KEYWORDS: Ultraviolet radiation, Lithography, Semiconducting wafers, Liquids, Process control, Optical lithography, Optical alignment, Etching, Nanoimprint lithography, Line edge roughness

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Proceedings Article | 16 June 2003 Paper

Paper

Design and performance of a step and repeat imprinting machine

Ian McMackin, Philip Schumaker, Daniel Babbs, Jin Choi, Wenli Collison, S. Sreenivasan, Norman Schumaker, Michael Watts, Ronald Voisin

Proceedings Volume 5037, (2003) https://doi.org/10.1117/12.490133

KEYWORDS: Semiconducting wafers, Etching, Ultraviolet radiation, Lithography, Liquids, Optical alignment, Particles, Critical dimension metrology, Scanning electron microscopy, Optical lithography

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Proceedings Article | 24 July 2002 Paper

Paper

New methods for fabricating step and flash imprint lithography templates

Douglas Resnick, Todd Bailey, David Mancini, Kevin Nordquist, William Dauksher, Eric Ainley, A. Talin, Kathleen Gehoski, Jeff Baker, Byung Choi, Stephen Johnson, Matthew Colburn, Mario Meissl, S. Sreenivasan, John Ekerdt, C. Grant Willson

Proceedings Volume 4608, (2002) https://doi.org/10.1117/12.437269

KEYWORDS: Etching, Chromium, Oxides, Semiconducting wafers, Quartz, Glasses, Scanning electron microscopy, Lithography, Printing, Photomasks

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Proceedings Article | 1 July 2002 Paper

Paper

High-resolution templates for step and flash imprint lithography

Douglas Resnick, William Dauksher, David Mancini, Kevin Nordquist, Eric Ainley, Kathleen Gehoski, Jeff Baker, Todd Bailey, Byung Choi, Stephen Johnson, S. Sreenivasan, John Ekerdt, C. Grant Willson

Proceedings Volume 4688, (2002) https://doi.org/10.1117/12.472293

KEYWORDS: Etching, Quartz, Chromium, Scanning electron microscopy, Photomasks, Semiconducting wafers, Glasses, Lithography, Printing, Oxides

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Proceedings Article | 20 August 2001 Paper

Paper

Layer-to-layer alignment for step and flash imprint lithography

Byung Choi, Mario Meissl, Matthew Colburn, Todd Bailey, Paul Ruchhoeft, S. Sreenivasan, F. Prins, Sanjay Banerjee, John Ekerdt, C. Grant Willson

Proceedings Volume 4343, (2001) https://doi.org/10.1117/12.436662

KEYWORDS: Optical alignment, Photomasks, Lithography, Semiconducting wafers, Overlay metrology, Liquids, Optical lithography, Ultraviolet radiation, Microscopes, Projection lithography

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Proceedings Article | 21 July 2000 Paper

Paper

Step and flash imprint lithography for sub-100-nm patterning

Matthew Colburn, Annette Grot, Marie Amistoso, Byung Choi, Todd Bailey, John Ekerdt, S. Sreenivasan, James Hollenhorst, C. Grant Willson

Proceedings Volume 3997, (2000) https://doi.org/10.1117/12.390082

KEYWORDS: Etching, Lithography, Optical lithography, Reactive ion etching, Silicon, Metals, Polymethylmethacrylate, Halogens, Semiconducting wafers, Ultraviolet radiation

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Showing 5 of 30 publications

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