Corner rounding improvement is critical to device performance, yield, and cell area reduction. In this paper, we present a method to use dual tone sub-resolution assist feature (SRAF) to improve both the outer corner rounding and inner corner rounding which in turn enhance the pattern quality. The simulation data and wafer data are presented. A few parameters have been investigated, such as the position of the SRAF, the shape of the SRAF, resist type and mask tone. The preliminary results show that more than 40% reduction of both inner corner rounding and outer corner rounding can be achieved by placing sub-resolution assist features at appropriate locations. The limit of corner rounding improvement is determined by mask rule check (MRC) and resist sensitivities.
As modern photolithography feature sizes reduce, the use of sub-resolution assist features (SRAFs) to improve the
manufacturing process window has become more prevalent. Beyond the assist features placement based on rules, a
model based assist feature (MBAF) flow is needed to optimize the shape and the size of SRAFs, so that the process
margin of the main features (MFs) is maximized. In the MBAF flow, a vital component is to build an accurate model
that specifically checks the printability of SRAFs, which are supposed to leave no trace on wafer. Compared to the
traditional optical proximity correction (OPC) model, the SRAF printability check model faces extra challenges, for
example, the small size of SRAFs makes their direct transfer to the mask pattern more difficult, the SRAFs are usually
not measurable on wafer and the worst-case SRAFs printability is typically at off-nominal conditions. In this paper, we
propose an innovative binary modeling method for SRAF printability check model, which does not require the
measurement of SRAFs' size on wafer and yet provides accurate prediction of SRAFs printing on wafer. In this
modeling method, the binary determination of whether an SRAF prints/does not print (i.e., clean) on wafer was acquired
by inspecting the SEMs taken from real wafer measurements. Then the local extrema of the signal intensity around the
SRAFs was simulated and used to classify print/clean groups of SRAFs, and a special cost function was designed to
separate the print SRAFs and clean SRAFs as much as possible during model calibration.
This paper presents a novel mask corner rounding (MCR) modeling approach based on Synopsys' Integrated Mask and
Optics (IMO) modeling framework. The point spread functions of single, double, and elliptical Gaussians are applied to
the IMO mask kernels to simulate MCR effects. The simulation results on two dimensional patterns indicate that the
aerial image intensity variation is proportional to the MCR induced effective area variations for single type corners. The
relationship may be reversed when multiple types of corners exist, where the corners close to the maximum intensity
region have a greater influence than others. The CD variations due to MCR can be estimated by the effective area
variation ratio and the image slope around the threshold. The good fitting results on line-end patterns indicate that the
ΔCD is the quadratic function of the Gaussian standard deviations. OPC modeling on 28nm-node contacts shows that
MCR has significant impact on model fitting results and process window controls. By considering the real mask
geometry effects and allowing in-line calibration of model parameters, the IMO simulation framework significantly
improves the OPC model accuracy, and maintains the calibration speed at a good level.
This paper presents a new etch-aware after development inspection (ADI) model with an inverse etch bias filter. We
model the etch bias as a function of pattern geometry parameters, and we introduce it to the ADI model by means of an
inverse bias matrix that works in conjunction with an ADI specification related matrix. The inverse bias filter tunes the
ADI model to be highly correlated to the etch effects and provides simplified and designable inputs to the after etch
inspection (AEI) model and hence improves its performance over the staged modeling flow. In addition, the inverse bias
filter creates a model based rule table for design retargeting. Some of the etch effects are corrected by the inverse bias
filter as the lithography model is calibrated, thus speeding up and simplifying the etch AEI model, while maintaining
lithography ADI model with a good accuracy.
This paper presents a new highly sensitive scatterometry based Probe-Pattern Grating (PPG) focus monitor and its
printing assessment on an advanced exposure tool. The high sensitivity is achieved by placing transparent lines spaced at
the strong focus spillover distance from the centerline of a 90 degree phase-shifted probe line that functions as an
interferometer detector. The monitor translates the focus error into the probe line trench depth, which can be measured
by scatterometry techniques. The sensitivity of the defocus measurement through scatterometry calibration is around
1.1nm defocus / nm trench depth. This result indicates that the PPG focus monitor from a single wafer focus setting can
detect the defocus distance to well under 0.05 Rayleigh Units.
Timely process characterization is crucial in Design for Manufacturing. Scatterometry as a powerful metrology tool can
be extended for optical system characterization. In this paper, we show how scatterometry can be used in conjunction
with an array of dual-pitch or dual-bar gratings to measure optical aberrations. Multiple pattern designs are presented
and compared. A linear model is used to describe the relation between aberration and measurable quantities. Firstprinciple
simulation results shows the current approach can simultaneously measure various Zernike coefficients with
accuracy ~2 mλ.
This paper proposes a new highly sensitive scatterometry based Probe-Pattern Grating Focus Monitor. The high
sensitivity is achieved by placing transparent lines spaced at the strong focus spillover distance of around 0.6λ/NA from
the centerline of a 90 degree phase-shifted probe line that functions as an interferometer detector. The monitor translates
the focus error into the probe line trench depth, which can be measured by scatterometry techniques. Simulations of
optical imaging, resist development and Optical Digital Profilometry measurements are used to evaluate the expected
practical performance. A linear model is developed to estimate focus error based on the measured probe trench depth.
The results indicate that the ODP measurement from a single wafer focus setting can detect both the defocus direction
and the defocus distance to well under 0.1 Rayleigh unit of defocus.
Earlier work describes the concept and the design of the Integrated Aerial Image Sensor (IAIS) . This paper focuses on the first principle modeling and the physical construction of the IAIS. Our modeling is based on Abbe's formulation. Assuming a partially coherent illumination source, the partial, total and final detector images are obtained through optical system simulations, combined with a wafer-plane aperture mask simulation, using software provided by Panoramic. The performance of the IAIS under different lithography settings can be predicted accordingly. Our intent is to create a library that captures the aerial image to detector image correspondence in order to facilitate rapid analysis. We also examine several approaches towards the integration of CCD chips onto the test wafer substrate. Although there are several issues that still need to be resolved, a low temperature bonding scheme involving capillary force assisted alignment appears quite promising and is being discussed in some detail.
The subject of this paper is a novel integrated aerial image sensor (IAIS) system suitable for integration within the surface of an autonomous test wafer. The IAIS could be used as a lithography processing monitor, affording a "wafer's eye view" of the process, and therefore facilitating advanced process control and diagnostics without integrating (and dedicating) the sensor to the processing equipment. The IAIS is composed of an aperture mask and an array of photo-detectors. In order to retrieve nanometer scale resolution of the aerial image with a practical photo-detector pixel size, we propose a design of an aperture mask involving a series of spatial phase "moving" aperture groups. We demonstrate a design example aimed at the 65nm technology node through TEMPEST simulation. The optimized, key design parameters include an aperture width in the range of 30nm, aperture thickness in the range of 70nm, and offer a spatial resolution of about 5nm, all with comfortable fabrication tolerances. Our preliminary simulation work indicates the possibility of the IAIS being applied to the immersion lithography. A bench-top far-field experiment verifies that our approach of the spatial frequency down-shift through forming large Moire patterns is feasible.