Source mask optimization (SMO) is widely used to make state-of-the-art semiconductor devices in high-volume manufacturing. To realize mature SMO solutions in production, the Intelligent Illuminator, which is an illumination system on a Nikon scanner, is useful because it can provide generation of freeform sources with high fidelity to the target. Proteus SMO, which employs co-optimization method and an insertion of validation with mask three-dimensional effect and resist properties for an accurate prediction of wafer printing, can take into account the properties of Intelligent Illuminator. We investigate an impact of the source properties on the SMO to pattern of a static random access memory. Quality of a source made on the scanner compared to the SMO target is evaluated with in-situ measurement and aerial image simulation using its measurement data. Furthermore, we discuss an evaluation of a universality of the source to use it in multiple scanners with a validation and with estimated value of scanner errors.
Source mask optimization (SMO) is widely used to make state-of-the-art semiconductor devices in high volume manufacturing. To realize mature SMO solutions in production, the Intelligent Illuminator, which is an illumination system on Nikon scanner, is useful because it can provide generation of freeform sources with high fidelity to the target. Proteus SMO, which employs co-optimization method and an insertion of validation with mask 3D effect and resist properties for an accurate prediction of wafer printing, can take into account the properties of Intelligent Illuminator. We investigate an impact of the source properties on the SMO to pattern of a static-random access memory. Quality of a source made on the scanner compared to the SMO target is evaluated with in-situ measurement and aerial image simulation using its measurement data. Furthermore we discuss an evaluation of a universality of the source to use it in multiple scanners with a validation with estimated value of scanner errors.
The transition into smaller nodes has resulted in stringent CD tolerance requirements and the role of mask LER in that budget is not sufficiently understood. The critical variables associated with mask LER were explored with the goal of establishing mask requirements based on wafer requirements. A systematic study of the impact of mask LER correlation length (ξ), critical exponent (α) and standard deviation of the line edge (σ) on the printability of 7nm node line/space (L/S) and contact holes (CH) in extreme ultraviolet lithography has been simulated. An experimentally relevant range of the three mask LER variables was explored in these simulations. CDU and CER/LER were the primary metrics used to gauge printability and they were evaluated as a function of ξ, α and σ with stochastic simulations. A 45nm pitch was investigated to determine critical mask LER parameters that mark printability transition regions relevant to the 7nm node middle of line.
Line width roughness remains a critical issue when moving towards smaller feature sizes in EUV lithography. We
present a stochastic resist modeling approach to accurately predict LWR and CD simultaneously. The stochastic model
simulates the roughness effects due to the shot noise and secondary electron effects during exposure, and the interaction
amongst the finite number of chemical molecules (inhibitor, PAG, quencher) during PEB. The model calibration used
the imec baseline EUV resist (Shinetsu SEVR140) with over 250 measured CDs and corresponding line width roughness
data. The validation was performed with 1D and 2D patterns. Especially for contact holes the predictability regarding
local CD uniformity is discussed. The good match between the simulations and wafer results for SRAM patterns further
exhibits the predictive power of the model. The model has been applied to simulate the new ASML NXE: 3100 EUV
conditions for both thin and thick absorber EUV masks. The comparison between the simulation results and wafer data
are reported.
Double Patterning (DP) is considered the most viable solution for printing features of the 32nm technology node using
193nm immersion lithography. Independent of the approach of the DP implementation (be it Litho-Etch-Litho-Etch or
Litho-Process-Litho-Etch), the second lithography step is influenced by the underlying topography on the wafer. Given
the tight constraints on the process, an accurate prediction of the impact of the embedded topography on critical features
is inevitable to meet the design requirements of the corresponding device layer. In this paper we use rigorous simulations
of the electro-magnetic field distribution to quantify the effect of wafer topography on the second lithography step. In
particular, we investigate the impact of the topography on CD control and corresponding process windows for typical 1D
patterns. The influence of non-flat BARC, non-flat resist surfaces, hard mask material and process variations in the first
litho step is simulated for dual line as well as dual trench processes. A metric to quantify standing waves in resist is
introduced and used to optimize BARC thickness. Further, we investigate typical 2D clips of decomposed mask layouts
relevant for the 32nm node. The simulation methodology and algorithm performance are presented, in particular with
respect to its distributed computing capabilities.
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