The model calibration process, in a resolution enhancement technique (RET) flow, is one of the most
critical steps towards building an accurate OPC recipe. RET simulation platforms use models for predicting
latent images in the wafer due to exposure of different design layouts. Accurate models can precisely
capture the proximity effects for the lithographic process and help RET engineers build the proper recipes
to obtain high yield. To calibrate OPC models, test geometries are created and exposed through the
lithography environment that we want to model, and metrology data are collected for these geometries.
This data is then used to tune or calibrate the model parameters. Metrology tools usually provide critical
dimension (CD) data and not edge placement error (EPE - the displacement between the polygon and resist
edge) data however model calibration requires EPE data for simulation. To work around this problem, only
symmetrical geometries are used since, having this constraint, EPE can be easily extracted from CD measurements.
In real designs, it is more likely to encounter asymmetrical structures as well as complex 2D structures that
cannot easily be made symmetrical, especially when we talk about technology nodes for 65nm and beyond.
The absence of 2D and asymmetric test structures in the calibration process would require models to
interpolate or extrapolate the EPE's for these structures in a real design.
In this paper we present an approach to extract the EPE information from both SEM images and contours
extracted by the metrology tools for structures on test wafers, and directly use them in the calibration of a
55nm poly process. These new EPE structures would now mimic the complexity of real 2D designs. Each
of these structures can be individually weighed according to the data variance. Model accuracy is then
compared to the conventional method of calibration using symmetrical data only. The paper also illustrates
the ability of the new flow to extract more accurate measurement out of wafer data that are more immune to
errors compared to the conventional method.
Overlay variations between different layers in Integrated Circuits fabrication can result in poor circuit performance, even
worst it can cause circuit mal function and consequently affect process yield. Coupled with other lithographic process
variations this effect can be highly magnified. This leads to the fact that searching for interconnects hot spots should
include overlay variations into account. The accuracy of inclusion of the overlay variation effect comes at the expense of
a more complex simulation setup. Many issues should be taken into consideration including runtime, process
combinations to be considered and the feasibility of providing a hint function for correction.
In this paper we present a systematic approach for classification of interconnects durability through the lithographic
process, taking into account focus, dose and overlay variations, the approach also provides information about the cause
for the low durability that can be useful for building a more robust design.
This classification can be accessible at the layout design level. With this information in hand, designers can test the
layout while building up their circuit. Modifications to the layout for higher interconnects durability can be easily made.
These modifications would be extremely expensive if they had to be made after design house tape out.
We verify this method by showing real wafer failures, due to bad interconnect design, against interconnects' durability
classifications from our method.
Ability to predict process behavior under defocus has until now relied on explicit calculations, which while accurate, cannot be realistically used in full-chip optical and process correction strategies due to the long run times. In this work, we have applied a vector model for the optics, and a compact model for the resist development process. Simulations with these models are fast enough to be the basis of full-chip OPC. We verify this strategy with an independent set of measurements, and compare it to current lithographic process fitting strategies. The results indicate that by describing optical processes as accurately as possible, the model accuracy improves over a wider range of defocus conditions when compared to the traditional calibration method. As long as the calibration process successfully decouples optical and resist effects, relatively simple resist models deliver excellent accuracy within the noise level of the metrology measurements. Our data are based on one-dimensional and two-dimensional results using a 193nm system using 0.75 NA and off axis illumination with 6% attenuated phase shift mask. In all cases, a wide variety of sub-resolution assist feature rules were used in order to further test the ability of the models to predict various optical and resist environments.
As 6% attenuated phase shift masks (PSM) become commonly used in ArF advanced lithography for the 90nm Technology and mass production to print lines/ spaces as well as contacts, the specification and control of the phase angle and the width of the distribution of phase angles becomes critical to maintain the quality of the lithography process. The influence of the mean phase angle and the width of the distribution of phase angles on the best focus, the through pitch behavior and uniformity of the critical dimension (CD uniformity) has been studied experimentally using a 6% attenuated PSM whose phase angle has been affected by several reticle cleans. The results are consistent with aerial image simulations. Independent specifications for the mean phase angle and the width of the distribution of phase angles have been derived and could be applied for the production of masks in the future.
Two fundamentally different approaches for chemical ArF resist shrinkage are evaluated and integrated into process flows for 90 nm technology node. The chemical shrink and the corresponding gain in process window is studied in detail for different resist types with respect to CD uniformity through pitch, linearity and resist profiles. For both, SAFIER and RELACS material, the sensitivity of the shrink process with respect to the baking temperature is characterized by a temperature matrix to check process stability, and optimized conditions are found offering an acceptable amount of
shrinkage at contact and trench levels. For the SAFIER material, thermal flow contributes to the chemical shrink which is a function of the photoresist chemistry and its hydrodynamic properties depending on the resists’ glass transition temperature (Tg) and the baking temperature: at baking temperatures close to Tg, a proximity and pattern dependent shrink is observed. For a given resist, line-space patterns and contact holes shrink differently, and their resist profiles are affected significantly. Additionally, the chemical shrinkage depends on the size of contact holes and resist profile prior to the application of the SAFIER process. At baking temperatures below Tg some resists exhibit no shrink at all. The
RELACS technique offers a constant shrink for contacts at various pitches and sizes. This shrink can be moderately adjusted and controlled by varying the mixing bake temperature which is generally and preferably below the glass transistion temperature of the resist, therefore no resist profile degradation is observed. A manufacturable process with a shrink of 20nm using RELACS at the contact layer is demonstrated. Utilizing an increased reticle bias in combination
with an increased CD target prior to the chemical shrink, the common lithography process window at contact layer was increased by 0.15um. The results also indicate a possibility for an extension of the shrink to greater than 50nm for more advanced processes.