For industrial print flaw detection images are acquired and then compared to a specimen (master image). Due to the
production process, the images are not exactly aligned to each other. Therefore, preceding a pixel-by-pixel comparison,
the acquired image has to be rectified in order to match the master image' properties-it has to be warped into the
master image' coordinate system. To achieve the required detection speed, several Megapixels per second have to be
processed. It proved to be very advantageous to continuously process the stream of image data in an image processing
pipeline. The first stage is the warping process. In this paper we introduce a streaming warper unit which implements
affine backward mapping and cubic spline interpolation. Since a complete pixel transformation is computed per clock
cycle the performance-implemented on contemporary FPGA
devices--can be up to 200 Megapixels per second. The
implementation of several streaming warper units within a single FPGA is possible. This enables image processing
systems which allow high data rates even under real-time constraints.
Dealing with high-speed image acquisition and processing systems, the speed of operation is often limited by the amount
of available light, due to short exposure times. Therefore, high-speed applications often use line-scan cameras, based on
charge-coupled device (CCD) sensors with time delayed integration (TDI). Synchronous shift and accumulation of
photoelectric charges on the CCD chip - according to the objects' movement - result in a longer effective exposure time
without introducing additional motion blur. This paper presents a high-speed color line-scan camera based on a
commercial complementary metal oxide semiconductor (CMOS) area image sensor with a Bayer filter matrix and a field
programmable gate array (FPGA). The camera implements a digital equivalent to the TDI effect exploited with CCD
cameras. The proposed design benefits from the high frame rates of CMOS sensors and from the possibility of arbitrarily
addressing the rows of the sensor's pixel array. For the digital TDI just a small number of rows are read out from the area
sensor which are then shifted and accumulated according to the movement of the inspected objects. This paper gives a
detailed description of the digital TDI algorithm implemented on the FPGA. Relevant aspects for the practical
application are discussed and key features of the camera are listed.
Today, printing products which must meet highest quality standards, e.g., banknotes, stamps, or vouchers, are automatically checked by optical inspection systems. Typically, the examination of fine details of the print or security features demands images taken from various perspectives, with different spectral sensitivity (visible, infrared, ultraviolet), and with high resolution. Consequently, the inspection system is equipped with several cameras and has to cope with an enormous data rate to be processed in real-time. Hence, it is desirable to move image processing tasks into the camera to reduce the amount of data which has to be transferred to the (central) image processing system. The idea is to transfer relevant information only, i.e., features of the image instead of the raw image data from the sensor. These features are then further processed. In this paper a color line-scan camera for line rates up to 100 kHz is presented. The camera is based on a commercial CMOS (complementary metal oxide semiconductor) area image sensor and a field programmable gate array (FPGA). It implements extraction of image features which are well suited to detect print flaws like blotches of ink, color smears, splashes, spots and scratches. The camera design and several image processing methods implemented on the FPGA are described, including flat field correction, compensation of geometric distortions, color transformation, as well as decimation and neighborhood operations.
Requirements for contemporary print inspection systems for industrial applications include, among others, high throughput, examination of fine details of the print, and inspection from various perspectives and different spectral sensitivity. Therefore, an optical inspection system for such tasks has to be equipped with several high-speed/high-resolution cameras, each acquiring hundreds of megabytes of data per second. This paper presents an inspection system which meets the given requirements by exploiting data parallelism and algorithmic parallelism. This is achieved by using complex field-programmable gate arrays (FPGA) for image processing. The scalable system consists of several processing modules, each representing a pair of a FPGA and a digital signal processor. The main chapters of the paper focus on the functionality implemented in the FPGA. The image processing algorithms include flat-field correction, lens distortion correction, image pyramid generation, neighborhood operations, a programmable arithmetic unit, and a geometry unit. Due to shortage of on-chip memory, a multi-port memory concept for buffering streams of data between off-chip and on-chip memories is used. Furthermore, performance measurements of the processing module are presented.
In this paper we present a new bus protocol satisfying extreme real time demands. It has been applied to a high
performance quality inspection system which can involve up to eight sensors of various types. Thanks to the modular
configuration this multi-sensor inspection system acts on the outside as a single sensor image processing system.
In general, image processing systems comprise three basic functions (i) image acquisition, (ii) image processing and (iii)
output of processed data. The data transfers for these three fundamental functions can be accomplished either by
individual bus systems or by a single bus. In case of using a single bus the system complexity of the implementation, i.e.
Development of protocols, hardware employment and EMC technical considerations, is far smaller. An important goal
of the new protocol design is to support extremely fast communication between individual processing modules. For
example, the input data (image acquisition) is transferred in real time to individual processing modules. Concurrent to
this communication the processed data are being transferred to the output module. Therefore, the key function of this
protocol is to realize concurrent data paths (data rates over 1.2 Gbit/s) by using principles of pipeline architectures and
methods of time division multiplex.
Moreover, the new bus protocol enables concurrent data transfers via a single bus system. In this paper the function of
the new bus protocol including hardware layout and innovative bus arbiter are described in details.
KEYWORDS: Digital signal processing, Real time imaging, Clocks, Imaging systems, Image processing, Computer programming, Signal processing, Software development, Algorithm development, Real time image processing
Although the hardware platform is often seen as the most important element of real-time imaging systems, software optimization can also provide remarkable reduction of overall computational costs. The recommended code development flow for digital signal processors based on the TMS320C6000(TM) architecture usually involves three phases: development of C code, refinement of C code, and programming linear assembly code. Each step requires a different level of knowledge of processor internals. The developer is not directly involved in the automatic scheduling process. In some cases, however, this may result in unacceptable code performance. A better solution can be achieved by scheduling the assembly code by hand. Unfortunately, scheduling of software pipelines by hand not only requires expert skills but is also time consuming, and moreover, prone to errors. To overcome these drawbacks we have designed an innovative development tool - the Software Pipeline Optimization Tool (SPOT(TM)). The SPOT is based on visualization of the scheduled assembly code by a two-dimensional interactive schedule editor, which is equipped with feedback mechanisms deduced from analysis of data dependencies and resource allocation conflicts. The paper addresses optimization techniques available by the application of the SPOT. Furthermore, the benefit of the SPOT is documented by more than 20 optimized image processing algorithms.