Electroabsorption from GeSi on silicon-on-insulator (SOI) is expected to have promising
potential for optical modulation due to its low power consumption, small footprint, and more
importantly, wide spectral bandwidth for wavelength division multiplexing (WDM) applications.
Germanium, as a bulk crystal, has a sharp absorption edge with a strong coefficient at the direct
band gap close to the C-band wavelength. Unfortunately, when integrated onto Silicon, or when
alloyed with dilute Si for blueshifting to the C-band operation, this strong Franz-Keldysh (FK)
effect in bulk Ge is expected to degrade. Here, we report experimental results for GeSi epi when
grown under a variety of conditions such as different Si alloy content, under selective versus non
selective growth modes for both Silicon and SOI substrates. We compare the measured FK effect
to the bulk Ge material.
Reduced pressure CVD growth of GeSi heteroepitaxy with various Si content was studied
by different characterization tools: X-ray diffraction (XRD), atomic force microscopy (AFM),
secondary ion mass spectrometry (SIMS), Hall measurement and optical transmission/absorption
to analyze performance for 1550 nm operation. State-of-the-art GeSi epi with low defect density
and low root-mean-square (RMS) roughness were fabricated into pin diodes and tested in a
surface-normal geometry. They exhibit low dark current density of 5 mA/cm2 at 1V reverse bias
with breakdown voltages of 45 Volts. Strong electroabsorption was observed in our GeSi alloy
with 0.6% Si content having maximum absorption contrast of Δα/α ~5 at 1580 nm at 75 kV/cm.
Silicon-based optical interconnects are expected to provide high bandwidth and low power consumption solutions for
chip-level communication applications, due to their electronics integration capability, proven manufacturing record and
attractive price volume curve. In order to compete with electrical interconnects, the energy requirement is projected to be
sub-pJ per bit for an optical link in chip to chip communication. Such low energies pose significant challenges for the
optical components used in these applications. In this paper, we review several low power photonic components
developed at Kotura for DARPA's Ultraperformance Nanophotonic Intrachip Communications (UNIC) project. These
components include high speed silicon microring modulators, wavelength (de)multiplexers using silicon cascaded
microrings, low power electro-optic silicon switches, low loss silicon routing waveguides, and low capacitance
germanium photodetectors. Our microring modulators demonstrate an energy consumption of ~ 10 fJ per bit with a drive
voltage of 1 V. Silicon routing waveguides have a propagation loss of < 0.3 dB/cm, enabling a propagation length of a
few tens of centimeters. The germanium photodetectors can have a low device capacitance of a few fF, a high
responsivity up to 1.1 A/W and a high speed of >30 GHz. These components are potentially sufficient to construct a full
optical link with an energy consumption of less than 1 pJ per bit.
Ring waveguide resonating structures with high quality factors are the key components servicing silicon
photonic links. We demonstrate highly efficient spectral tunability of the microphotonic ring structures
manufactured in commercial 130 nm SOI CMOS technology. Our rings are fitted with dedicated heaters
and integrated with silicon micro-machined features. Optimized layout and structure of the devices result in
their maximized thermal impedance and increased efficiency of the thermal tuning.
Silicon photonics is envisioned as a promising solution to address the interconnect bottleneck
in large-scale multi-processor computing systems, owing to advantageous attributes such as wide
bandwidth, high density, and low latency. To leverage these advantages, optical proximity coupler is
one of the critical enablers. Chip-to-chip, layer-to-layer optical proximity couplers with low loss,
large bandwidth, small footprint and integration compatibility are highly desirable. In this paper, we
demonstrate chip-to-chip optical proximity coupling using grating couplers. We report the
experimental results using grating couplers fabricated in a photonically-enabled commercial 130nm
SOI CMOS process.
We present a hybrid integration technology platform for the compact integration of best-in-breed VLSI and photonic
circuits. This hybridization solution requires fabrication of ultralow parasitic chip-to-chip interconnects on the candidate
chips and assembly of these by a highly accurate flip-chip bonding process. The former is achieved by microsolder bump
interconnects that can be fabricated by wafer-scale processes, and are shown to have average resistance <1 ohm/bump
and capacitance <25fF/bump. This suite of technologies was successfully used to hybrid integrate high speed VLSI chips
built on the 90nm bulk CMOS technology node with silicon photonic modulators and detectors built on a 130nm
CMOS-photonic platform and an SOI-photonic platform; these particular hybrids yielded Tx and Rx components with
energies as low as 320fJ/bit and 690fJ/bit, respectively. We also report on challenges and ongoing efforts to fabricate
microsolder bump interconnects on next-generation 40nm VLSI CMOS chips.
Scaling of high performance, many-core, computing systems calls for disruptive solutions to provide ultra energy
efficient and high bandwidth density interconnects at very low cost. Silicon photonics is viewed as a promising solution.
For silicon photonics to prevail and penetrate deeper into the computing system interconnection hierarchy, it requires
innovative optical devices, novel circuits, and advanced integration. We review our recent progress in key building
blocks toward sub pJ/bit optical link for inter/intra-chip applications, ultra-low power silicon photonic transceivers. In
particular, compact reverse biased silicon ring modulator was developed with high modulation bandwidth sufficient for
15Gbps modulation, very small junction capacitance of ~50fF, low voltage swing of 2V, high extinction ratio (>7dB)
and low optical loss (~2dB at on-state). Integrated with low power CMOS driver circuits using low parasitic microsolder
bump technique, we achieved record low power consumption of 320fJ/bit at 5Gbps data rate. Stable operation with biterror-
rate better than 10-13 was accomplished with simple thermal management. We further review the first hybrid
integrated silicon photonic receiver based on Ge waveguide photo detector using the same integration technique, with
which high energy efficiency of 690fJ/bit, and sensitivity of ~18.9dBm at 5Gbps data rate for bit-error-rate of 10-12 were
Ring waveguide resonating structures with high quality factors are the key components in the silicon photonics portfolio
boosting up its functionality and circuit performance. Due to a number of manufacturing reasons their peak wavelengths
are often prone to deviate from designed values. In order to keep the ring resonator operating as specified, its peak
wavelength then needs to be corrected in a reliable and power efficient way. We demonstrate the performance of the
thermally tunable mux/demux filter ring structures fabricated in the commercial 130 nm SOI CMOS line.
In this paper we present a computing system that uniquely leverages the bandwidth, density, and
latency advantages of silicon photonic interconnects to enable highly compact supercomputerscale
systems. We present the details of an optically enabled "macrochip" which is a set of
contiguous, optically-interconnected chips that deploy wavelength-division multiplexed (WDM)
enabled by silicon photonics. We describe the system architecture and the WDM point-to-point
network implementation of a "macrochip" providing bisection bandwidth of 10 TBps and discuss
system and device level challenges, constraints, and the critical technologies needed to implement
this system. We present a roadmap to lowering the energy-per-bit of a silicon photonic
interconnect and highlight recent advances in silicon photonics under the UNIC program that
facilitate implementation of a "macrochip" system made of arrayed chips.
The Ultra-performance Nanophotonic Intrachip Communication (UNIC) project aims to achieve unprecedented high-density,
low-power, large-bandwidth, and low-latency optical interconnect for highly compact supercomputer systems.
This project, which has started in 2008, sets extremely aggressive goals on power consumptions and footprints for
optical devices and the integrated VLSI circuits. In this paper we will discuss our challenges and present some of our
first-year achievements, including a 320 fJ/bit hybrid-bonded optical transmitter and a 690 fJ/bit hybrid-bonded optical
receiver. The optical transmitter was made of a Si microring modulator flip-chip bonded to a 90nm CMOS driver with
digital clocking. With only 1.6mW power consumption measured from the power supply voltages and currents, the
transmitter exhibits a wide open eye with extinction ratio >7dB at 5Gb/s. The receiver was made of a Ge waveguide
detector flip-chip bonded to a 90nm CMOS digitally clocked receiver circuit. With 3.45mW power consumption, the
integrated receiver demonstrated -18.9dBm sensitivity at 5Gb/s for a BER of 10-12. In addition, we will discuss our
Mux/Demux strategy and present our devices with small footprints and low tuning energy.
We report a very compact (1.6μmx10μm) and low dark current (20nA) Germanium p-i-n photodetector integrated on
0.25μm thick silicon-on-insulator (SOI) waveguides. A thin layer of Germanium was selective-epitaxially grown on top
of SOI waveguides. Light is evanescently coupled into Germanium layer from the bottom SOI waveguide. The device
demonstrates superior performance with demonstrated responsivity of 0.9A/W and 0.56A/W at wavelength of 1300nm
and 1550nm, respectively, and dark current less than 20nA at -0.5V bias. The 3dB bandwidth of the device is measured
to be 23GHz at -0.5V bias.
We review the progress and challenges in scaling computing systems; discuss the
potential benefits and challenges for achieving optical-interconnects to the chip via the
native integration of silicon photonics components with VLSI electronics; and introduce
the "macrochip" - a collection of contiguous silicon chips enabled by optical proximity
We introduce a novel approach to interconnect multiple chips together with a silicon
photonic WDM point-to-point network enabled by optical proximity communications to act as a
single large piece of logical silicon much larger than a single reticle limit. We call this structure a
macrochip. This non-blocking network provides all-to-all low-latency connectivity while
maximizing bisection bandwidth, making it ideal for multi-core and multi-processor
interconnections. We envision bisection bandwidth up to TBps for an 8x8 macrochip design. And a
5-6x improvement in latency can be achieved when compared to a purely electronic implementation.
We also observe better overall performance over other optical network architectures.
We review 10Gb/sec Optical Proximity Communication realized with packaged chips that carry SOI
optical waveguides and reflecting mirrors micromachined in silicon. The high precision chip to chip
alignment and placement was enabled by a new packaging concept based on the co-integration of
pyramidal pit features defined by anisotropic silicon etch and matching high precision micro-spheres. We
support this novel packaging approach with measured optical transmission data and discuss the extent of it
towards other applications of Proximity Communication.