Proc. SPIE. 11328, Design-Process-Technology Co-optimization for Manufacturability XIV
KEYWORDS: Visual analytics, Fin field effect transistors, Error analysis, Manufacturing, Clouds, Extreme ultraviolet, Transistors, Integrated circuit design, System on a chip, Electronic design automation
As the semiconductor industry strives to keep Moore’s Law moving forward, companies are continually confronted with new and mounting challenges. The use of fin field-effect transistors (finFETs) and the recent introduction of gate-allaround (GAA) finFETs present questions of performance, scalability, and variation resilience that have yet to be fully resolved. The need for multi-patterning, which has been in place since the 22 nm node, is not going away, even with the introduction of extreme ultraviolet (EUV) lithography. Complex fill requirements have emerged as a critical success factor in both manufacturability and performance in leading-edge nodes. These factors, among others, have created significant impacts across the electronic design automation (EDA) design-to-tapeout ecosystem, particularly in physical verification. In response, EDA suppliers constantly evaluate and experiment with the design information they receive from both design houses and foundries, and often establish collaborative projects, to assess the impact of changing technology, and to develop and implement new functionality and new tools that reduce or eliminate time and resource impacts while ensuring accuracy and full coverage. Replacing inefficient, less precise verification processes with smarter, more accurate, faster, and more efficient functionality helps maintain, and even grow, both the bottom line and product quality in the face of increasing technological complexity.
Electronic circuit designers commonly start their design process with a schematic, namely an abstract representation of the physical circuit. In integrated photonics on the other hand, it is very common for the design to begin at the physical component level. In order to build large integrated photonic systems, it is crucial to design using a schematic-driven approach. This includes simulations based on schematics, schematic-driven layout, layout versus schematic verification, and post-layout simulations. This paper describes such a design framework implemented using Mentor Graphics and Lumerical Solutions design tools. In addition, we describe challenges in silicon photonics related to manufacturing, and how these can be taken into account in simulations and how these impact circuit performance.
This paper describes design methodologies developed for silicon photonics integrated circuits. The approach presented is inspired by methods employed in the Electronics Design Automation (EDA) community. This is complemented by well established photonic component design tools, compact model synthesis, and optical circuit modelling. A generic silicon photonics design kit, as described here, is available for download at http://www.siepic.ubc.ca/GSiP.
As designs grow more complex, process technologies become smaller, and geometry counts increase, the work required to achieve acceptable yeild becomes increasingly demanding and difficult. Underlying this state of affairs is the need to maximize yield without increasing manufacturing costs. This paper addresses techniques for increasing yield as well as suggestions for determining whether yield enhancement techniques are cost effective.