Nanotechnology can be seen to already have an impact on IC processing, no matter how it is defined. Nanomanipulators can be used for a variety of tasks in investigating nanostructures. An emerging application is the probing of individual transistors at the contact level anywhere on a die. As downscaling continues its inexorable march with the increasingly strong optical and other processing proximity effects, the ability to collect IV data from individual transistors anywhere in the circuit is becoming a valuable tool for failure analysis, yield enhancement, reliability, process integration, and time to market. The talk will discuss current capabilities and a roadmap to improve the productivity and capabilities of nanoprobing technology. In the longer term, nanotechnology's impact will not be on characterization and testing, but on processing itself. The real promise of nanotechnology is unprecedented process control of all phases of fabrication. An approach to atomically precise manufacturing will be presented that could enable the fabrication of Si or Si/Ge devices where dopant atoms can be precisely placed and the dimensions and control of those dimensions are limited only by the crystal lattice and its reconstruction due to surface or lattice strain. This fabrication technology could be used to produce ultra-scaled CMOS or advanced device technology.
Zyvex is developing a low-cost high-precision method for manufacturing MEMS-based three-dimensional structures/assemblies. The assembly process relies on compliant properties of the interconnecting components. The sockets and connectors are designed to benefit from their compliant nature by allowing the mechanical component to self-align, i.e. reposition themselves to their designed, stable position, independent of the initial placement of the part by the external robot. Thus, the self-aligning property guarantees the precision of the assembled structure to be very close to, or the same, as the precision of the lithography process itself.
A three-dimensional (3D) structure is achieved by inserting the connectors into the sockets through the use of a passive end-effector. We have developed the automated, high-yield, assembly procedure which permits connectors to be picked up from any location within the same die, or a separate die. This general procedure allows for the possibility to assemble parts of dissimilar materials.
We have built many 3D MEMS structures, including several 3D MEMS devices such as a scanning electron microscope (SEM) micro column, mass-spectrometer column, variable optical attenuator. For these 3D MEMS structures we characterize their mechanical strength through finite element simulation, dynamic properties by finite-element analysis and experimentally with UMECH’s MEMS motion analyzer (MMA), alignment accuracy by using an in-house developed dihedral angle measurement laser autocollimator, and impact properties by performing drop tests. The details of the experimental set-ups, the measurement procedures, and the experimental data are presented in this paper.
In the face of Moore's Law, the lithographic community is finding increasing pressure to do more with less. More, in the sense that lithographers are expected to use an exposure wavelength "lambda" that is shrinking at a slower rate than the critical dimensions (CDs) of devices. This has resulted in the introduction of complicated Resolution Enhancement Technology (RET) schemes. Less, in the sense that the competitive marketplace has resulted in shortened development cycles. These shortened development times mean that lithography and RET teams are often expected to demonstrate "first pass success" with increasing complex lithographic solutions. Unfortunately, first silicon on product prototypes may reveal deficiencies in an OPC infrastrcuture which had been developed using only research and development (R&D) testdie. The primary cause of these deficiencies is that the development and test-structure layouts frequently lack the 2D complexity of real circuitry. OPC models and lithography R&D traditionally compensate well for failures and marginal sites on the simple patterns of R&D testdie. The more complex geometries of real layouts frequently present new challenges. Here, we describe a program initiated at TI to add a complex pattern to the very first test reticle generated for a new technology node. This pattern is auto-generated and includes a random combination of representive circuits at the design rule for that node. OPC is applied to the pattern almost immediately after layout. The distribtion of printed features and marginal sites can then be identified early using simulation. Scanning Electron Microscope (SEM) images of resist and post-etch features can further identify sites requiring changes once reticles are received. We have shown that this early OPC R&D on complex geometries can prevent several OPC revision cycles and enable faster volume yield ramp.
Selective strong phase shift mask techniques, whereby a phase-shift mask exposure is followed by a binary mask exposure to define a single pattern, present unique capabilities and problems. First, there is the proper exposure balance and alignment of the two masks. Second, there is the challenge of performing optical proximity correction that will account for two overlaying exposure models and masks. This is further complicated by the need to perform multiple biasing and adjustments that are often required for development processes. In this paper, we present results for applying a new OPC correction technique to a dual exposure binary and phase-shift mask that have been used for development of 100 nm CMOS processes. The correction recipe encompasses two models that were anchored to optimized processes (exposure, NA, and ?). The correction to the masks also utilized boolean techniques to perform selective biasing without destroying the original hierarchical structure. CMOS technology utilizes isolation with pitches of active device regions below 0.4 ?m. The effective gate length on silicon is in the range of 0.08 to 0.18 ?m. Patterning of trench openings and gate regions are accomplished using deep-UV lithography.
The aggressive schedule for downscaling of gate dimensions and need for tight CD control for the 130nm node has created the need to seriously consider the use of a Levenson phase shift mask with 248nm lithography tools. The improvements in exposure latitude and depth of focus of strong phase shift over binary patterning are well known and have been clearly demonstrated. What is less well understood is the impact of the mask error factor.
Two lithography strategies - of alternating PSM using double expose method (DEM) and high transmission attenuated PSM - were investigated to assess their capability for printing 0.1 micrometers gate. In order to do that, the optimization of each process has been carried out for maximizing the process window; of depth of focus (DOF) and expose latitude (EL), to make them satisfy process requirement generated by focus and expose budget study. The key components of optimization are finding the best NA and sigma, the optimum bias for isolated lines and dense lines and the optimum transmission of att PSM. Then, the impacts of some critical lithographic parameters such as phase error effects in APSM, proximity effects and mask error factor (MEF) were determined with experimental data. As final answer to the question of process capability of two lithography techniques for 0.1 micrometers gate patterning, CD control analysis was made to see if they satisfy our gate CD control requirements.
The timing of 193nm tools and the resist to support them is driving semiconductor manufacturers to plan for production of sub-half lambda features on 248nm exposure tools. Lithographers are turning to reticle enhancements to close the capability gap, finding that there are a myriad of issues that must be addressed to achieve production- worthiness.
This paper discuses the need for additional mask quality factors for implementation into a further roadmap. These factors are expected to affect the printed image on wafer. Especially the global idea of pattern fidelity is introduced. Low voltage scanning electron microscopy can offer the capability to mask makers to deliver this extra information. This knowledge should lead to a better understanding how mask imperfections may contribute to the overall lithography error budget. This understanding will need to rely on stronger collaboration between mask maker and mask user. Using simulation data and the so-called mask error factor, it is shown that certain mask strategies may allow larger mask error budgets.
We study the problems of (1) pattern-dependent, (2) thermal, and (3) bonding distortion in stencil masks for ion projection lithography. (1) Pattern-dependent distortion was found to consist mainly of a correctable magnification error in representative circularly symmetric masks whose amplitude is determined by the size and average density of the pattern. After magnification correction, distortion decreases rapidly with increasing modulation frequency, falling to values below 5 nm for spatial frequencies greater than 0.23 cycles/mm. (2) We show that the use of a cold cylinder to enhance radiation cooling can limit temperatures to within 1.5 K of 300 K over the surface of 120 mm membrane. This minimizes pattern-dependent, conductive heat flow and reduces distortion to below 10 nm. (3) An aluminum metallic bonding technology is described for attaching silicon support rings to membranes with a radial bonding stress below 1 MPa. We conclude that the most serious potential distortion problems for silicon stencil masks should have practical solutions.
Ion projection lithography (IPL) is analogous to an optical wafer stepper except the exposing photons have been replaced by high energy, light ions. In the IPL machine being developed by the Advanced Lithography Group (ALG), a silicon stencil mask is `illuminated' by a broad area beam of hydrogen or helium ions. The ions pass through stencil mask openings and enter a multi-electrode electrostatic lens system which projects a demagnified image of the stencil mask onto a resist coated wafer substrate. Demonstrated IPL performance is covered. Independent calculations of the novel ion-optical column of the ALG prototype tool show less than 15 nm distortion over a 20 mm X 20 mm field, and indicate that even larger fields are possible. This machine will utilize standard optical, off-axis, wafer alignment and a precision laser interferometer controlled X-Y-stage. This combined `pattern lock' will enable the ALG prototype to achieve overlay requirements necessary for 0.15 micrometers geometries. The Advanced Lithography Group project for constructing the prototype ion projector is discussed.
It has recently been demonstrated[1,2] that zero-dimensional semiconductor
structures ("quantum dots") can be fabricated with electrical contact to
individual dots, and that the current voltage characteristics correspond to
tunneling through the discrete density of states of a zero-dimensional
system. Because the density of states in such a quantum dot is a series of
delta functions there is the potential for sharp transitions between tunneling
and non-tunneling (on and off) states in devices fabricated from quantum
dots. Such devices therefore could form the basis of a post-VLSI integrated
These quantum dot devices are laterally-confined variations on the resonant
tunneling diode (RTD). RTDs consist of a two dimensional quantum well
surrounded by tunnel barriers. RTDs exhibit current peaks when electron
energies in their contacts are aligned with quantum states in the well. As
the quantum well states drop below the emitter conduction band edge, the
current falls and there is negative differential resistance (NDR). Quantum dot
diodes (QDDs) are RTDs which have lateral dimensions small enough to split
the sub-bands in the quantum well into discrete energy states. This lateral
confinement also creates 1-d sub-bands in the contact regions adjacent to the
dot which become one dimensional quantum wires, leading to a more complex
situation than exists in large area RTDs.
This paper describes recent developments in three areas ofmasked ion beam lithography (MIBL). These are 1) fabrication
oflarge area, low distortion, silicon stencilmasks for demagnifying ion projection lithography, 2) fabrication ofstencil masks
with nanometer scale resolution for 1:1 proximity printing, and 3) development of a direct method of alignment using the
ion beam induced fluorescence of Si02. These topics are discussed below.
Demagnifying ion projection masks: We describe the fabrication of stencil masks in large area, low stress (10 MPa), n-type
silicon membranes. The projection masks have a silicon foil area 95 mm in diameter, thicknesses between 1.5-5 and
resolution of0.6um. Measured distortion (3a) in the IPL masks ranges between 0.23gm and 0.65,um, with an experimental
error of 0.20 1um.
Proximity printing masks: A process is described for fabricating stencil masks with 50 nm resolution in low stress, n-type
silicon membranes. Membranes less than 0.5 ,ttm thick are shown to be free of the sidewall taper that limits resolution in
thicker masks. These thin membranes show a slightly flared profile due to the imperfectly collimated etching ions.
Alignment: A direct method of alignment is being developed which uses the ion beam induced fluorescence of Si02 marks.
Fluorescence yield is characterized as a function of ion energy and resist coating thickness. The yield for Si02 is in the range
between 0.1-1.0 photons/proton, while the yields for Si, Al, and photoresist are negligibly small. Thus, a simple alignment
technique can be implemented where registration of a grating in the mask with a corresponding oxide pattern is detected
as a fluorescence maximum. A simple model predicts that 50 nm alignment can be accomplished, following a 1 im
prealignment, in 2 seconds.