Dr. John C. Robinson Profile

Dr. John C. Robinson

Director at KLA Corporation

SPIE Involvement:

Senior status | Conference Program Committee | Author

Area of Expertise:

Metrology , Process Control , Physics , Inspection , Semiconductor Manufacturing , LED

Websites:

Company Website | Personal Website

Publications (44)

SPIE Journal Paper | November 30, 2018

Special Section Guest Editorial: Control of Integrated Circuit Patterning Variance, Part 3: Pattern Roughness, Local Uniformity, and Stochastic Defects

John C. Robinson, Tim Brunner, Gian Lorusso

JM3 Vol. 17 Issue 04

KEYWORDS: Stochastic processes, Optical lithography, Integrated circuits, Line edge roughness, Extreme ultraviolet lithography, Line width roughness, Metrology, Critical dimension metrology, Photomasks, Semiconducting wafers

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PROCEEDINGS ARTICLE | April 27, 2018

Spectral tunability for accuracy, robustness, and resilience

Proc. SPIE. 10585, Metrology, Inspection, and Process Control for Microlithography XXXII

KEYWORDS: Apodization, Metrology, Polarization, Laser scattering, Quality measurement, Scatterometry, Image quality, Laser metrology, Semiconducting wafers, Overlay metrology

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In overlay (OVL) metrology the quality of measurements and the resulting reported values depend heavily on the measurement setup used. For example, in scatterometry OVL (SCOL) metrology a specific target may be measured with multiple illumination setups, including several apodization options, two possible laser polarizations, and multiple possible laser wavelengths. Not all possible setups are suitable for the metrology method as different setups can yield significantly different performance in terms of the accuracy and robustness of the reported OVL values. Finding an optimal measurement setup requires great flexibility in measurement, to allow for high-resolution landscape mapping (mapping the dependence of OVL, other metrics, and details of pupil images on measurement setup). This can then be followed by a method for analyzing the landscape and selecting an accurate and robust measurement setup. The selection of an optimal measurement setup is complicated by the sensitivity of metrology to variations in the fabrication process (process variations) such as variations in layer thickness or in the properties of target symmetry. The metrology landscape changes with process variations and maintaining optimal performance might require continuous adjustments of the measurement setup. Here we present a method for the selection and adjustment of an optimal measurement setup. First, the landscape is measured and analyzed to calculate theory-based accurate OVL values as well as quality metrics which depend on details of the pupil image. These OVL values and metrics are then used as an internal ruler (“self-reference”), effectively eliminating the need for an external reference such as CD-SEM. Finally, an optimal measurement setup is selected by choosing a setup which yields the same OVL values as the self-reference and is also robust to small changes in the landscape. We present measurements which show how a SCOL landscape changes within wafer, wafer to wafer, and lot to lot with intentionally designed process variations between. In this case the process variations cause large shifts in the SCOL landscape and it is not possible to find a common optimal measurement setup for all wafers. To deal with such process variations we adjust the measurement setup as needed. Initially an optimal setup is chosen based on the first wafer. For subsequent wafers the process stability is continuously monitored. Once large process variations are detected the landscape information is used for selecting a new measurement setup, thereby maintaining optimal accuracy and robustness. Methods described in this work are enabled by the ATL (Accurate Tunable Laser) scatterometry-based overlay metrology system.

PROCEEDINGS ARTICLE | March 13, 2018

In-cell overlay metrology by using optical metrology tool

Proc. SPIE. 10585, Metrology, Inspection, and Process Control for Microlithography XXXII

KEYWORDS: Optical imaging, Metrology, Diffractive optical elements, Etching, Optical metrology, Process control, Semiconducting wafers, Overlay metrology, Model-based design, Process modeling

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PROCEEDINGS ARTICLE | March 13, 2018

Clean focus, dose and CD metrology for CD uniformity improvement

Proc. SPIE. 10585, Metrology, Inspection, and Process Control for Microlithography XXXII

KEYWORDS: Signal to noise ratio, Metrology, Modulation, Scanners, Scatterometry, Process control, Finite element methods, Critical dimension metrology, Semiconducting wafers, Single crystal X-ray diffraction

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PROCEEDINGS ARTICLE | March 28, 2017

High-volume manufacturing device overlay process control

Proc. SPIE. 10145, Metrology, Inspection, and Process Control for Microlithography XXXI

KEYWORDS: Metrology, Data modeling, Scanners, Inspection, Control systems, Scanning electron microscopy, Optical inspection, Process control, Semiconductor manufacturing, High volume manufacturing, Semiconducting wafers, Optics manufacturing, Overlay metrology

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PROCEEDINGS ARTICLE | March 28, 2017

Patterned wafer geometry grouping for improved overlay control

Proc. SPIE. 10145, Metrology, Inspection, and Process Control for Microlithography XXXI

KEYWORDS: Semiconductors, Metrology, Optical lithography, Principal component analysis, Seaborgium, Manufacturing, Inspection, Control systems, Process control, Semiconductor manufacturing, Optical alignment, Semiconducting wafers, Tolerancing, Overlay metrology

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PROCEEDINGS ARTICLE | March 18, 2016

Application of overlay modeling and control with Zernike polynomials in an HVM environment

Proc. SPIE. 9778, Metrology, Inspection, and Process Control for Microlithography XXX

KEYWORDS: Metrology, Optical lithography, Data modeling, Image processing, Scanners, Control systems, Zernike polynomials, Process control, High volume manufacturing, Semiconducting wafers, Yield improvement, Overlay metrology

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PROCEEDINGS ARTICLE | March 18, 2016

Advanced overlay: sampling and modeling for optimized run-to-run control

Proc. SPIE. 9778, Metrology, Inspection, and Process Control for Microlithography XXX

KEYWORDS: Mathematical modeling, Metrology, Data modeling, Scanners, Process control, High volume manufacturing, Semiconducting wafers, Overlay metrology

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In recent years overlay (OVL) control schemes have become more complicated in order to meet the ever shrinking margins of advanced technology nodes. As a result, this brings up new challenges to be addressed for effective run-to- run OVL control. This work addresses two of these challenges by new advanced analysis techniques: (1) sampling optimization for run-to-run control and (2) bias-variance tradeoff in modeling. The first challenge in a high order OVL control strategy is to optimize the number of measurements and the locations on the wafer, so that the “sample plan” of measurements provides high quality information about the OVL signature on the wafer with acceptable metrology throughput. We solve this tradeoff between accuracy and throughput by using a smart sampling scheme which utilizes various design-based and data-based metrics to increase model accuracy and reduce model uncertainty while avoiding wafer to wafer and within wafer measurement noise caused by metrology, scanner or process. This sort of sampling scheme, combined with an advanced field by field extrapolated modeling algorithm helps to maximize model stability and minimize on product overlay (OPO). Second, the use of higher order overlay models means more degrees of freedom, which enables increased capability to correct for complicated overlay signatures, but also increases sensitivity to process or metrology induced noise. This is also known as the bias-variance trade-off. A high order model that minimizes the bias between the modeled and raw overlay signature on a single wafer will also have a higher variation from wafer to wafer or lot to lot, that is unless an advanced modeling approach is used. In this paper, we characterize the bias-variance trade off to find the optimal scheme. The sampling and modeling solutions proposed in this study are validated by advanced process control (APC) simulations to estimate run-to-run performance, lot-to-lot and wafer-to- wafer model term monitoring to estimate stability and ultimately high volume manufacturing tests to monitor OPO by densely measured OVL data.

PROCEEDINGS ARTICLE | March 18, 2016

Device overlay method for high volume manufacturing

Proc. SPIE. 9778, Metrology, Inspection, and Process Control for Microlithography XXX

KEYWORDS: Metrology, Transparency, Optical lithography, Data modeling, Image processing, Inspection, Control systems, Scanning electron microscopy, Optical metrology, Process control, High volume manufacturing, Semiconducting wafers, Overlay metrology

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PROCEEDINGS ARTICLE | March 19, 2015

HVM capabilities of CPE run-to-run overlay control

Proc. SPIE. 9424, Metrology, Inspection, and Process Control for Microlithography XXIX

KEYWORDS: Metrology, Optical parametric oscillators, Scanners, Error analysis, Control systems, Process control, High volume manufacturing, Semiconducting wafers, Yield improvement, Overlay metrology

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PROCEEDINGS ARTICLE | March 19, 2015

High order overlay modeling and APC simulation with Zernike-Legendre polynomials

Proc. SPIE. 9424, Metrology, Inspection, and Process Control for Microlithography XXIX

KEYWORDS: Mathematical modeling, Data modeling, Scanners, Zernike polynomials, Process control, Feedback control, Semiconducting wafers, Statistical modeling, Performance modeling, Overlay metrology

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Feedback control of overlay errors to the scanner is a well-established technique in semiconductor manufacturing [1]. Typically, overlay errors are measured, and then modeled by least-squares fitting to an overlay model. Overlay models are typically Cartesian polynomial functions of position within the wafer (Xw, Yw), and of position within the field (Xf, Yf). The coefficients from the data fit can then be fed back to the scanner to reduce overlay errors in future wafer exposures, usually via a historically weighted moving average. In this study, rather than using the standard Cartesian formulation, we examine overlay models using Zernike polynomials to represent the wafer-level terms, and Legendre polynomials to represent the field-level terms. Zernike and Legendre polynomials can be selected to have the same fitting capability as standard polynomials (e.g., second order in X and Y, or third order in X and Y). However, Zernike polynomials have the additional property of being orthogonal over the unit disk, which makes them appropriate for the wafer-level model, and Legendre polynomials are orthogonal over the unit square, which makes them appropriate for the field-level model. We show several benefits of Zernike/Legendre-based models in this investigation in an Advanced Process Control (APC) simulation using highly-sampled fab data. First, the orthogonality property leads to less interaction between the terms, which makes the lot-to-lot variation in the fitted coefficients smaller than when standard polynomials are used. Second, the fitting process itself is less coupled – fitting to a lower-order model, and then fitting the residuals to a higher order model gives very similar results as fitting all of the terms at once. This property makes fitting techniques such as dual pass or cascading [2] unnecessary, and greatly simplifies the options available for the model recipe. The Zernike/Legendre basis gives overlay performance (mean plus 3 sigma of the residuals) that is the same as standard Cartesian polynomials, but with stability similar to the dual-pass recipe. Finally, we show that these properties are intimately tied to the sample plan on the wafer, and that the model type and sampling must be considered at the same time to demonstrate the benefits of an orthogonal set of functions.

PROCEEDINGS ARTICLE | April 14, 2014

Run time scanner data analysis for HVM lithography process monitoring and stability control

Proc. SPIE. 9050, Metrology, Inspection, and Process Control for Microlithography XXVIII

KEYWORDS: Lithography, Statistical analysis, Visual analytics, Data modeling, Visualization, Scanners, Atomic force microscopy, Optical alignment, Semiconducting wafers, Data analysis

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PROCEEDINGS ARTICLE | April 2, 2014

Integrated production overlay field-by-field control for leading edge technology nodes

Proc. SPIE. 9050, Metrology, Inspection, and Process Control for Microlithography XXVIII

KEYWORDS: Optical lithography, Data modeling, Scanners, Error analysis, Control systems, Atomic force microscopy, Process control, Semiconducting wafers, Statistical modeling, Overlay metrology

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PROCEEDINGS ARTICLE | April 2, 2014

In-line focus monitoring and fast determination of best focus using scatterometry

Proc. SPIE. 9050, Metrology, Inspection, and Process Control for Microlithography XXVIII

KEYWORDS: Semiconductors, Lithography, Optical design, Metrology, Matrices, Scanners, Scatterometry, Finite element methods, Semiconducting wafers, Scatter measurement

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PROCEEDINGS ARTICLE | April 18, 2013

Study of overlay in EUV/ArF mix and match lithography

Proc. SPIE. 8681, Metrology, Inspection, and Process Control for Microlithography XXVII

KEYWORDS: Lithography, Metrology, Scanners, Control systems, Photomasks, Extreme ultraviolet, Extreme ultraviolet lithography, Semiconducting wafers, Overlay metrology, Personal protective equipment

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PROCEEDINGS ARTICLE | April 5, 2012

Weighted least squares regression for advanced overlay control

Proc. SPIE. 8324, Metrology, Inspection, and Process Control for Microlithography XXVI

KEYWORDS: Lithography, Optical filters, Metrology, Data modeling, Manufacturing, Control systems, Process control, Integrated circuits, Semiconducting wafers, Overlay metrology

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PROCEEDINGS ARTICLE | April 5, 2012

Overlay control methodology comparison: field-by-field and high-order methods

Proc. SPIE. 8324, Metrology, Inspection, and Process Control for Microlithography XXVI

KEYWORDS: Lithography, Metrology, Data modeling, Scanners, Composites, Control systems, Process control, Semiconducting wafers, Overlay metrology, Standards development

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PROCEEDINGS ARTICLE | April 5, 2012

Data feed-forward for improved optical CD and film metrology

Proc. SPIE. 8324, Metrology, Inspection, and Process Control for Microlithography XXVI

KEYWORDS: Metrology, Dielectrics, 3D modeling, Optical metrology, Time metrology, Process control, High volume manufacturing, Critical dimension metrology, Semiconducting wafers, Optics manufacturing

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PROCEEDINGS ARTICLE | April 20, 2011

High-order stitching overlay analysis for advanced process control

Proc. SPIE. 7971, Metrology, Inspection, and Process Control for Microlithography XXV

KEYWORDS: Metrology, Optical lithography, Statistical analysis, Data modeling, Scanners, Distortion, Process control, Semiconducting wafers, Statistical modeling, Overlay metrology

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PROCEEDINGS ARTICLE | April 20, 2011

Improved overlay control using robust outlier removal methods

Proc. SPIE. 7971, Metrology, Inspection, and Process Control for Microlithography XXV

KEYWORDS: Semiconductors, Metrology, Data modeling, Numerical simulations, Data processing, Process control, Semiconductor manufacturing, Semiconducting wafers, Overlay metrology, Instrument modeling

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PROCEEDINGS ARTICLE | March 29, 2011

Mask registration impact on intrafield on-wafer overlay performance

Proc. SPIE. 7971, Metrology, Inspection, and Process Control for Microlithography XXV

KEYWORDS: Lithography, Reticles, Optical lithography, Scanners, Error analysis, Image registration, Photomasks, Double patterning technology, Semiconducting wafers, Overlay metrology

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PROCEEDINGS ARTICLE | April 2, 2010

Improved scanner matching using scanner fleet matcher (SFM)

Proc. SPIE. 7638, Metrology, Inspection, and Process Control for Microlithography XXIV

KEYWORDS: Electronics, Metrology, Phase modulation, Scanners, Distortion, Atomic force microscopy, Software development, Semiconducting wafers, Performance modeling, Overlay metrology

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PROCEEDINGS ARTICLE | April 2, 2010

Mask registration and wafer overlay

Proc. SPIE. 7638, Metrology, Inspection, and Process Control for Microlithography XXIV

KEYWORDS: Metrology, Scanners, Distortion, Image registration, Pellicles, Distance measurement, Photomasks, Double patterning technology, Semiconducting wafers, Overlay metrology

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PROCEEDINGS ARTICLE | April 2, 2010

Automated optimized overlay sampling for high-order processing in double patterning lithography

Proc. SPIE. 7638, Metrology, Inspection, and Process Control for Microlithography XXIV

KEYWORDS: Mathematical modeling, Lithography, Metrology, Optical lithography, Data modeling, Photomasks, Double patterning technology, Semiconducting wafers, Statistical modeling, Overlay metrology

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PROCEEDINGS ARTICLE | March 10, 2010

Simultaneous optimization of dose and focus controls in advanced ArF immersion scanners

Proc. SPIE. 7640, Optical Microlithography XXIII

KEYWORDS: Data modeling, Scanners, Error analysis, Control systems, Scatterometry, Finite element methods, Neural networks, Critical dimension metrology, Semiconducting wafers, Scatter measurement

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PROCEEDINGS ARTICLE | March 24, 2009

Improve scanner matching using automated real-time feedback control via scanner match maker (SMM)

Proc. SPIE. 7272, Metrology, Inspection, and Process Control for Microlithography XXIII

KEYWORDS: Metrology, Optical lithography, Phase modulation, Scanners, Inspection, Distortion, Process control, Feedback control, Semiconducting wafers, Overlay metrology

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PROCEEDINGS ARTICLE | March 24, 2009

The study and simulation of high-order overlay control including field-by-field methodologies

Proc. SPIE. 7272, Metrology, Inspection, and Process Control for Microlithography XXIII

KEYWORDS: Semiconductors, Lithium, Optical lithography, Data modeling, Scanners, Control systems, Semiconductor manufacturing, Optical alignment, Semiconducting wafers, Overlay metrology

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PROCEEDINGS ARTICLE | March 24, 2009

Advanced modeling strategies to improve overlay control for 32-nm lithography processes

Proc. SPIE. 7272, Metrology, Inspection, and Process Control for Microlithography XXIII

KEYWORDS: Lithography, Data modeling, Visualization, Scanners, Double patterning technology, Immersion lithography, Semiconducting wafers, Radium, Performance modeling, Overlay metrology

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PROCEEDINGS ARTICLE | March 23, 2009

Sampling for advanced overlay process control

Proc. SPIE. 7272, Metrology, Inspection, and Process Control for Microlithography XXIII

KEYWORDS: Lithography, Optical lithography, Control systems, Monte Carlo methods, Time metrology, Process control, Immersion lithography, Statistical methods, Semiconducting wafers, Overlay metrology

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PROCEEDINGS ARTICLE | April 16, 2008

Sampling for advanced overlay process control

Proc. SPIE. 6922, Metrology, Inspection, and Process Control for Microlithography XXII

KEYWORDS: Lithography, Metrology, Optical lithography, Scanners, Error analysis, Fourier transforms, Time metrology, Process control, Semiconducting wafers, Overlay metrology

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PROCEEDINGS ARTICLE | March 26, 2008

A system to optimize mix-and-match overlay in lithography

Proc. SPIE. 6922, Metrology, Inspection, and Process Control for Microlithography XXII

KEYWORDS: Lithography, Reticles, Phase modulation, Databases, Scanners, Distortion, Semiconducting wafers, Factor analysis, Overlay metrology, Distributed interactive simulations

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PROCEEDINGS ARTICLE | March 25, 2008

In-line focus-dose monitoring for hyper NA imaging

Proc. SPIE. 6922, Metrology, Inspection, and Process Control for Microlithography XXII

KEYWORDS: Lithography, Metrology, Diffractive optical elements, Data modeling, Scanners, 3D modeling, Finite element methods, Neural networks, Photoresist processing, Semiconducting wafers

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PROCEEDINGS ARTICLE | April 5, 2007

Litho cell control using MPX

Proc. SPIE. 6518, Metrology, Inspection, and Process Control for Microlithography XXI

KEYWORDS: Wafer-level optics, Reticles, Metrology, Data modeling, Calibration, Image processing, Scanners, Finite element methods, Semiconducting wafers, Wafer testing

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PROCEEDINGS ARTICLE | April 5, 2007

Improved overlay control through automated high order compensation

Proc. SPIE. 6518, Metrology, Inspection, and Process Control for Microlithography XXI

KEYWORDS: Lithography, Reticles, Databases, Scanners, Error analysis, Control systems, Distortion, Optical alignment, Semiconducting wafers, Overlay metrology

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PROCEEDINGS ARTICLE | March 24, 2006

An integrated approach to the determination of a manufacturable process window in advanced microlithography

Proc. SPIE. 6152, Metrology, Inspection, and Process Control for Microlithography XX

KEYWORDS: Lithography, Metrology, Manufacturing, Electroluminescence, Scanning electron microscopy, Process control, Finite element methods, Design for manufacturing, Semiconducting wafers, Resolution enhancement technologies

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PROCEEDINGS ARTICLE | May 10, 2005

Utilizing overlay target noise metrics for improved process control

Proc. SPIE. 5752, Metrology, Inspection, and Process Control for Microlithography XIX

KEYWORDS: Metrology, Statistical analysis, Metals, Image processing, Diagnostics, Process control, Semiconducting wafers, Overlay metrology, Process modeling, Visibility

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PROCEEDINGS ARTICLE | May 24, 2004

A comparison of methods for in-chip overlay control at the 65-nm node

Proc. SPIE. 5375, Metrology, Inspection, and Process Control for Microlithography XVIII

KEYWORDS: Lithography, Reticles, Metrology, Data modeling, Scanners, Error analysis, Data acquisition, Semiconducting wafers, Overlay metrology, Personal protective equipment

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PROCEEDINGS ARTICLE | May 24, 2004

Scanner overlay mix and match matrix generation: capturing all sources of variation

Proc. SPIE. 5375, Metrology, Inspection, and Process Control for Microlithography XVIII

KEYWORDS: Metrology, Data modeling, Phase modulation, Matrices, Scanners, Error analysis, Optical alignment, Semiconducting wafers, Statistical modeling, Overlay metrology

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PROCEEDINGS ARTICLE | April 29, 2004

Yield loss in lithographic patterning at the 65nm node and beyond

Proc. SPIE. 5378, Data Analysis and Modeling for Process Control

KEYWORDS: Lithography, Metrology, Manufacturing, Process control, Spectroscopic ellipsometry, Photomasks, Critical dimension metrology, Semiconducting wafers, Overlay metrology, Resolution enhancement technologies

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PROCEEDINGS ARTICLE | June 2, 2003

Performance study of new segmented overlay marks for advanced wafer processing

Proc. SPIE. 5038, Metrology, Inspection, and Process Control for Microlithography XVII

KEYWORDS: Lithography, Optical design, Metrology, Optical lithography, Data modeling, Metals, Image segmentation, Semiconducting wafers, Overlay metrology, Imaging metrology

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PROCEEDINGS ARTICLE | June 2, 2003

Lithography and metrology overlay troubleshooting by advanced query and multivariate analysis

Proc. SPIE. 5038, Metrology, Inspection, and Process Control for Microlithography XVII

KEYWORDS: Lithography, Metrology, Statistical analysis, Data modeling, Databases, Metals, Semiconducting wafers, Overlay metrology, Back end of line, Data analysis

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PROCEEDINGS ARTICLE | August 22, 2001

Characterization of optical proximity correction features

Proc. SPIE. 4344, Metrology, Inspection, and Process Control for Microlithography XV

KEYWORDS: Lithography, Reticles, Optical lithography, Etching, Scanning electron microscopy, Photomasks, Optical proximity correction, Critical dimension metrology, Semiconducting wafers, Tolerancing

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PROCEEDINGS ARTICLE | June 2, 2000

Manufacturing considerations for implementation of scatterometry for process monitoring

Proc. SPIE. 3998, Metrology, Inspection, and Process Control for Microlithography XIV

KEYWORDS: Metrology, Silicon, Manufacturing, Reflectivity, Atomic force microscopy, Scanning electron microscopy, Scatterometry, Process control, Critical dimension metrology, Semiconducting wafers

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PROCEEDINGS ARTICLE | June 14, 1999

Characterization of overlay tolerance requirements for via to metal alignment

Proc. SPIE. 3677, Metrology, Inspection, and Process Control for Microlithography XIII

KEYWORDS: Oxides, Metals, Copper, Resistance, Scanning electron microscopy, Optical alignment, Critical dimension metrology, Tolerancing, Overlay metrology, Electrical breakdown

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