In this work we apply a new laser scanning apparatus in multiple ways to measure various aspects of in-process and final silicon-on-insulator (SOI) wafers in high volume manufacturing (HVM). The laser scanner enables high-spatialresolution whole-wafer metrology of topographic features, film thickness variation, and two scattering channels, while bridging between 200 mm and 300 mm diameters on a single platform.
Proc. SPIE. 9778, Metrology, Inspection, and Process Control for Microlithography XXX
KEYWORDS: Lithography, Polishing, Metrology, Digital signal processing, Spatial frequencies, Image processing, Manufacturing, Linear filtering, Data processing, Process control, Convolution, High volume manufacturing, Semiconducting wafers, Surface finishing, Overlay metrology, Chemical mechanical planarization, Front end of line
One requirement for advanced lithography remains suitable incoming wafer topography. We propose that local wafer flatness be visualized and quantified using the techniques developed for wafer front-surface nanotopography. This is a significant change in that existing wafer topography metrology tools do not enable our proposed approach.
Air pockets (APK) occur randomly in Czochralski (Cz) grown silicon (Si) crystals and may become included in wafers after
slicing and polishing. Previously the only APK of interest were those that intersected the front surface of the wafer and
therefore directly impacted device yield. However mobile and other electronics have placed new demands on wafers to
be internally APK-free for reasons of thermal management and packaging yield. We present a novel, recently patented,
APK image processing technique and demonstrate the use of that technique, off-line, to improve quality control during
Flatness of the incoming silicon wafer is one major contributor to the ultimate focusing limitation of modern exposure tools. Exposure tools are designed to chuck wafers without creating non-flatness and then use focus control to follow as closely as possible the chucked wafer front surface topography. The smaller size of the exposure slit in a step-and-scan exposure tool, as compared to the previous generation full-field stepper tool, helps minimize the impact of chucked wafer non-flat topography. However, to maintain high throughput and improve critical dimension uniformity (CDU) at sub-wavelength line-widths requires continuous improvement in the incoming silicon wafer flatness. In this paper we report extensive experimental results that review existing wafer flatness metrics and propose the addition of a new metric. The new metric emulates the scanning motion of exposure by integrating the defocus that each point on the wafer experiences during exposure. We show that this method is in better spatial agreement with measured defocus in step-and-scan exposure tools. Simple metrics of moving average (MA) defocus prediction analysis will be defined and shown to correlate very well to post exposure defocus data. These experiments were enabled by the creation of special 300-nm wafers by MEMC. These special wafers include sites with a wide variation in flatness. Prior to exposure the wafers were measured with a high-resolution optical flatness metrology tool (WaferSight by ADE) to obtain industry standard thickness variation (flatness) data. Incoming wafer flatness data is used to predict wafer suitability for lithography at the desired device geometry node (e.g., 90 nm). The flatness data was processed and characterized using both standard metrics (SFQR) and the new MA analysis. The relationship between the industry standard metric (SFQR) and similar metrics applied to MA analysis will be presented. Full two-dimensional maps are used to present spatial correlations and permit simple physical insights into the flatness data sets. Measurements of chucked wafer flatness were made on the same wafers using ASML TWINSCAN in-line metrology. These measurements correlate very well to thickness-based flatness. Un-chucked wafer flatness metrics (SFQR and MA) are shown to correlate well to post exposure defocus data when an appropriate site size is used. This result is discussed in relationship to the industry-accepted practice of specifying un-chucked wafer flatness. Lithography performance tests were made to prove the relevance of the different flatness metrics. The same special wafers are used for lithography performance tests. These tests achieve excellent correlation between post-exposure full-wafer focus control results and predictions based on both SFQ (industry standard) and MA re-mapping of the flatness data. The relationship between measured critical dimension (CD) and defocus is also explored. Point-by-point analysis of CD residual versus measured defocus data nicely follows a Bossung curve. We also show that residual CD values predicted from defocus correlate well with measured values. These experiments confirm the application of industry standard wafer flatness measurements to step-and-scan lithography when appropriately using current metrics. They also present the potential for improved metrics based on the MA defocus prediction analysis to help drive continuous improvement of wafer flatness for advanced step-and-scan lithography.
Wafer dimensional metrology, used to qualify substrates for lithography at the appropriate critical dimensions (CDs), historically reports shape and flatness. While these metrics have enabled several generations of educated wafer procurement, the high numerical aperture (NA) lithography required for sub-wavelength CDs now in production is becoming sensitive to front surface topography that is not reported by either shape or flatness. SEMI Standard M43, Guide for Reporting Wafer Nanotopography, is now published. According to this guide, 'Nanotopography is the non-planar deviation of the whole front wafer surface within a spatial wavelength range of approximately 0.2 to 20 mm and within the fixed quality area.' These nanometer scale non-planar deviations lead to within-die, die-to-die, and wafer-to- wafer variation that contributes to the overall focal budget. Several advanced CMOS device manufactures are no specifying incoming wafer nanotopography. These manufacturers all produce complex, high-speed, large die- size chips. In the following we detail wafer nanotopography metrology and nanotopography quantification. We also explore several known correlations of nanotopography to leading edge process integration issues.
According to industry standards (SEMI M43, Guide for Reporting Wafer Nanotopography), Nanotopography is the non- planar deviation of the whole front wafer surface within a spatial wavelength range of approximately 0.2 to 20 mm and within the fixed quality area (FQA). The need for precision metrology of wafer nanotopography is being actively addressed by interferometric technology. In this paper we present an approach to mapping the whole wafer front surface nanotopography using an engineered coherence interferometer. The interferometer acquires a whole wafer raw topography map. The raw map is then filtered to remove the long spatial wavelength, high amplitude shape contributions and reveal the nanotopography in the filtered map. Filtered maps can be quantitatively analyzed in a variety of ways to enable statistical process control (SPC) of nanotopography parameters. The importance of tracking these parameters for CMOS gate level processes at 180-nm critical dimension, and below, is examined.
Self-focusing leads to bifurcations of transverse solitary waves in sodium vapor (2D) and to second-order spatial solitons in a GaAs planar waveguide gain medium (1D). Transverse patterns in vertical-cavity surface-emitting lasers are shown to contain field vortices under some conditions. Good agreement is found between experimental data and computations.
An approach to optical interconnect networks at the module level is presented that addresses the requirements imposed by electronic system manufacturing, such as thermal stability, low cost, and compatibility with standard electronic design, fabrication, and assembly processes. Research is presented on poled polyimide electro-optic materials with extended thermal stability, poled polyimide integrated optic switches acting as transmitters, and a demonstration of a CMOS-compatible optical interconnect.
We report the background leading to the development of the first all-polyimide system (cladding/core/cladding) suitable for fabrication of electro-optic waveguide devices on silicon substrates. The cladding layers are spun from a low optical loss, commercially available polyimide that is suitable for multilayer stacks. The electro-optic material consists of this same polyimide as host to a commercially available guest chromophore and is based upon our prior work on thermoplastic polyimides. The synthesis and purification of this chromophore and an analog is discussed. We also present the materials and process development methodology with the results for this polymer system and demonstrate it by fabrication of an all-polyimide Mach- Zehnder modulator operating at 830 nm. CMOS-compatible switching using a device based on the new material has been demonstrated.
The exceptional electro-optic properties of poled polymer films, coupled with the power and flexibility of thin film fabrication and photolithographic processing, may make possible the hybrid integration of electronic and photonic devices, combining the processing power of VLSI with a dense, high bandwidth, photonic interconnection and switching network in a single, large format, package. In this paper, we describe the potential applications and benefits of electro-optic polymers for optical interconnection and present a review of some of the relevant progress to date in electro-optic polymer materials and devices. Development of an all-polyimide electro-optic polymer system (cladding/core/cladding) based entirely on commercially available components is described. An integrated optic Mach-Zehnder modulator was fabricated using this material system and used in a 200 Mbit/sec digital signal transmission optical interconnection demonstration. Lastly, a potential increase in electro-optic polymer integration density was illustrated by a proof of concept demonstration of three levels of waveguide structures on a single substrate.
Bifurcations of optical transverse solitary waves are studied for one-way propagation through a sodium vapor cell. Two types of phase encoding seed transverse bifurcations resulting in cell- exit profiles with beauty rivaling that of a kaleidoscope. The cell-exit profiles are stationary in time, reproduce completely when the power or frequency is scanned, and agree well with one- way computations. Temporal and longitudinal development of the cell-exit profiles is shown, demonstrating both the instability nature of this phenomenon and its solitary wave nature. The first evidence is also presented for a double-peaked Raman gain
Using polyimide as host in a guest-host electro-optic thin film a thermally stable poled electro- optic response is demonstrated at temperatures at 150 degree(s)C and 300 degree(s)C. A coplanar-electrode poling geometry is used so that the guest molecular alignment between the electrodes is coincident with the free volume of the host. Electric field poling during curing process including imidization (170 - 230 degree(s)C) and densification (340 - 380 degree(s)C) accounts for the highly thermally stable electro-optic response.
The exceptional electro-optic properties of poled polymer films, coupled with the power and flexibility of thin film fabrication and photolithographic processing, may make possible a new class of integrated optic systems: photonic large scale integration (PLSI). PLSI systems are characterized by the hybrid integration of electronic and photonic devices, combining the processing power of VLSI with a dense, high bandwidth, photonic interconnection and switching network in a single, large format, package. In this paper, we describe the potential applications and benefits of PLSI and present a review of some of the relevant progress to date in electro-optic polymer materials and devices, including the demonstration of polymer switch based 100 Mbit/sec digital signal transmission for optical interconnection and a 20 GHz electro-optic polymer modulator.
We present transient measurements of the electro-optic response and the heterodyne technique used
to monitor the poling process in-situ. Several of the measurements presented are made on a low-dopinglevel
guest-host polymer to facilitate comparison with theory. Also presented are measurements on a
stable poled side-chain polymer. The data indicate response rise and fall times of the order of milliseconds
for the guest-host sample and the temperature dependence of those times is compared to the theoretical
model. Good qualitative agreement between theory and experimental data is presented.