As the lithography design rule of IC manufacturing industry migrates into sub-130nm nodes, low k1 factor prevails, the mask error enhancement factor (MEEF) increases. Low k1 processing calls for aggressive sub-resolution assist features and the use of attenuated phase shift masks (AttPSMs). The aggressive OPC features pose challenges to reticle inspection due to high false detection, which is time-consuming for defect classification and impacts the throughput of mask manufacturing. Moreover, the high transmission of the shifter material of 193 nm AttPSM also challenges the UV-based reticle inspection tools with high nuisance counts due to undesirable optical diffraction effects. For a given reticle inspection tool, it is necessary to calibrate the system contrast between the clear and opaque regions (quartz/chrome or quartz/MoSi) of the reticles. In this study, we present the influences of various calibration conditions on sensitivity, false and nuisance detection of reticle inspections. Both the STARlight contamination inspections and the die-to-die pattern inspections were carried out using the KLA-Tencor TeraStar inspection tools with production masks and programmed defect test masks including binary intensity masks (BIMs) and AttPSMs. Successful applications with low false detection and adapted sensitivity will be illustrated in terms of optimizing the calibration setup.
Inspection of aggressive OPC represents one of the major challenges for today's mask inspection methodologies. Systems are phased with high-density layouts, containing OPC features far below the resolution limit of conventional inspection systems. This causes large amounts of false and nuisance defects, especially on production applications. The paper presents the use of Aera193, a new inspection system using aerial imaging as inspection methodology.
In the IC industry the mask cost and cycle time have increased dramatically since the chip design has become more complex and the required mask specification, tighter. The lithography technology has been driven to 65-nm node and 90-nm product will be manufacturing in 2004, according to ITRS's roadmap. However, the optical exposure tools do not extend to a shorter wavelength as the critical dimension (CD) shrinks. In such sub-wavelength technology generation,
the mask error factor (MEF) is normally higher. Higher MEF means that tighter mask specification is required to sustain the lithography performance. The tighter mask specification will impact both mask processing complexity and cost. The mask is no longer a low-cost process. In addition, the number of wafers printed from each mask set is trending down, resulting in a huge investment to
tape out a new circuit. Higher cost discourages circuit shrinking, thus, prohibits commercialization of new technology nodes.
The paper presents a revolutionary technology to inspect advanced contact layers. Instead of finding defects based on a size-dependent defect specification, defects are found according to their impact at the wafer CD result. The inspection methodology used is aerial imaging. The main advantage of this method is that only defects, which actually affect the wafer result, will be detected and classified. The paper presents first inspection results on contact layers designed for the 130nm and 90 nm technology node.
Following mask inspection, mask-defect classification is a process of reviewing and classifying each captured defect according to prior-defined printability rules. With the current hardware configuration in manufacturing environments, this review and classification process is a mandatory manual task. For cases with a relatively small number of captured defects, defect classification itself does not put too much burden to operators or engineers. With a moderate increase of defects, it would however, become a time-consuming process and prolong the total mask-making cycle time. Should too many nuisance defects be caught under a given detection sensitivity, engineers would generally loosed the detection sensitivity in order to reduce the number of nuisance defects. By doing that however, there exists potential threat of missing real defects. The present study describes a 'progressive self-learning' (PSL) algorithm for defect classification to relieve loading from operators or engineers and further accelerate defect review/classification process. Basically, the PSL algorithm involves with image extraction, digitization, alignment and matching. One key concept of this PSL algorithm is that there is not any pre-stored defect library in the first place of a particular run. In turn, a defect library is 'progressively' built during the initial stage of defect review and classification at each run. The merit of this design can be realized by its flexibility. An additional benefit is that all defect images are stored and suitable for network transfer. The C language is adopted to implement the present algorithm to avoid the porting issue, so as not bound to a particular machine. Assessment of the PSL algorithm is examined in terms of efficiency and the accurate rate.
Conference Committee Involvement (4)
19 September 2006 | Monterey, California, United States
3 October 2005 | Monterey, California, United States
14 September 2004 | Monterey, California, United States
9 September 2003 | Monterey, California, United States