NASA's Wide-Field Infrared Survey Telescope (WFIRST) project has developed the ACADIA ASIC, a next generation detector control and acquisition system-on-a-chip. The purpose of this ASIC is to address the stringent requirements of operating a cryogenic detector in a spacecraft environment. Key performance criteria are low analog noise and low power consumption at temperatures between 150K and 180K while supporting the full dynamic range of the sensor. The ASIC is primarily intended to operate the Teledyne H4RG for WFIRST, but has been designed with considerable flexibility to provide compatibility with a large selection of other detectors. Up to 40 analog sensor outputs can processed in parallel, where each signal is amplified and conditioned by a low-noise pre-amplifier with programmable gain and bandwidth, and then digitized by a 16-bit successive approximation analog-to-digital converter (ADC). The ASIC includes 24 analog output channels that can be configured as programmable voltage or current sources, and are used to generate biases and references to the detector. A simple-to-program sequencer provides timing control for the detector and the ASIC internal circuits, with the option of using an embedded microprocessor for more elaborate readout schemes. This paper presents an overview of the ACADIA ASIC design with detailed descriptions of its analog, mixedsignal, and digital circuit blocks. First prototypes of the ACADIA ASIC have been fabricated, and preliminary test results of functionality and performance have been measured. We discuss the test environment and the obtained results, and conclude by describing the next steps for the project. The ACADIA ASIC is intended to operate the Teledyne H4RG infrared hybrid detector (current baseline for the WFIRST Wide-Field Instrument), but has been designed with considerable flexibility to provide compatibility with a large selection of other detectors. Each analog sensor output is amplified and conditioned by a low-noise pre-amplifier with programmable gain and bandwidth, and then digitized by a 16-bit successive approximation analog-to-digital converter (ADC). Up to 40 signals can be processed in parallel. Some basic math functions like summing, averaging, threshold comparison, and digital gain are available per channel. In addition, the ASIC includes 24 analog output channels that can be configured as programmable voltage or current sources, and are used to provide biases and references to the detector. Overall timing control is provided by a flexible but simple-to-program sequencer, with the option of microprocessor control for more elaborate readout schemes. Further digital capabilities include Direct Memory Access (DMA) engine, timers, Serial Peripheral Interface (SPI), and science data formatting for transmission. All circuitry has been protected against single event effects from ionizing radiation. We will discuss the status of the development effort, with focus on the performance requirements, general design features, and available test results. Over the course of the development, several test chips have been built that have already demonstrated significant improvements in analog performance over prior solutions, and have shown compliance with key WFIRST requirements for both cryogenic and room temperature operation. Prototypes of the full 40-channel ACADIA ASIC have been fabricated and are currently being tested. In addition to the chip itself, the packaging approach, test environment, and control electronics with computer acquisition will be presented.
Snowballs are transient events observed in HgCdTe detectors with a sudden increase of charge in a few pixels. They appear between consecutive reads of the detector, after which the affected pixels return to their normal behavior. The origin of the snowballs is unknown, but it was speculated that they could be the result of alpha decay of naturally radioactive contaminants in the detectors, but a cosmic ray origin cannot be ruled out. Even though previous studies predicted a low rate of occurrence of these events, and consequently, a minimal impact on science, it is interesting to investigate the cause or causes that may generate snowballs and their impact in detectors designed for future missions. We searched for the presence of snowballs in the dark current data in Euclid and Wide Field Infrared Survey Telescope (WFIRST) detectors tested in the Detector Characterization Laboratory at Goddard Space Flight Center. Our investigation shows that for Euclid and WFIRST detectors, there are snowballs that appear only one time, and others than repeat in the same spatial localization. For Euclid detectors, there is a correlation between the snowballs that repeat and bad pixels in the operational masks (pixels that do not fulfill the requirements to pass spectroscopy, photometry noise, quantum efficiency, and/or linearity). The rate of occurrence for a snowball event is about 0.9 snowballs/hr. in Euclid detectors (for the ones that do not have associated bad pixels in the mask), and about 0.7 snowballs/hr. in PV3 Full Array Lot WFIRST detectors.
The Wide-Field Infrared Survey Telescope (WFIRST) will have the largest near-IR focal plane ever flown by NASA, a total of 18 4K x 4K devices. The project has adopted a system-level approach to detector control and data acquisition where 1) control and processing intelligence is pushed into components closer to the detector to maximize signal integrity, 2) functions are performed at the highest allowable temperatures, and 3) the electronics are designed to ensure that the intrinsic detector noise is the limiting factor for system performance. For WFIRST, the detector arrays operate at 90 to 100 K, the detector control and data acquisition functions are performed by a custom ASIC at 150 to 180 K, and the main data processing electronics are at the ambient temperature of the spacecraft, notionally ~300 K. The new ASIC is the main interface between the cryogenic detectors and the warm instrument electronics. Its single-chip design provides basic clocking for most types of hybrid detectors with CMOS ROICs. It includes a flexible but simple-to-program sequencer, with the option of microprocessor control for more elaborate readout schemes that may be data-dependent. All analog biases, digital clocks, and analog-to-digital conversion functions are incorporated and are connected to the nearby detectors with a short cable that can provide thermal isolation. The interface to the warm electronics is simple and robust through multiple LVDS channels. It also includes features that support parallel operation of multiple ASICs to control detectors that may have more capability or requirements than can be supported by a single chip.
Raytheon Vision Systems (RVS) has been developing high performance low background VisSWIR focal plane arrays suitable for the NASA WFIRST mission. These near infrared sensor chip assemblies (SCAs) are manufactured using HgCdTe on CdZnTe substrates with a 10 micron pixel pitch. WFIRST requirements are for a 4k x 4K format 4-side buttable package to populate a large scale 6 x 3 mosaic focal plane array of 18 SCAs. RVS devices will be compatible with the NASA developed FPA 4-side buttable package, and flight interface electronics. Initial development efforts at RVS have focused on a 2k x 2k format 10 micron pixel design based on an existing readout integrated circuit (ROIC) to demonstrate desired detector material performance at a relevant scale. This paper will provide performance results on the RVS efforts. RVS has successfully developed multiple 4k x 4k 10 micron pixel ROICs and we plan to demonstrate readiness to scale our design efforts to the desired 4k x 4k format for WFIRST in 2016.