Data technology for data handling, correction, and verification has become the essential technology of photomask. By the shrinkage of device pitch and the development of lithography technology, the data volume of photomask has been increased continuously and the correction and verification technology based on design data has an important role to meet the target of patterning quality. Especially, because EUV lithography makes single patterning possible, the decrease of device pitch rises to the challenge on the data technology for EUV photomask. Furthermore, the multi-beam mask writer which enables dose modulation for each pixel requires fundamental changes such as data format, data flow, and correction algorithm. Here, we will discuss about 7 kinds of data technologies and one proposal for the era of EUV lithography.
In EUV Lithography, mask shadowing effect and photon shot noise effect are the main sources of patterning limit,
critical dimension (CD) non-uniformity and low imaging properties. In this paper, the patterning performance of a 6%
attenuated phase shift mask (PSM) is valuated, and the results show that this can be used for half-pitch (hp) down to 14 nm with 0.33NA due to the improved stochastic patterning properties. The proposed PSM consists of 26.5 nm of TaN as an absorber layer and 14 nm of Mo as a phase shifter on 2.5 nm thick Ru capped Mo/Si multilayers. This structure has ~6% reflectivity at the absorber stack and 180° phase shift. The improved stochastic resist patterning properties of PSM were compared with those of conventional binary intensity mask (BIM) with a 70 nm-thick TaN absorber for the 14 ~ 22 nm line and space (L/S) 1:1 dense pattern with 0.33NA off-axis illumination conditions with a EUV generic resist model.
The Electron Optical System (EOS) is designed for the electron beam machine employing a vector scanned variable shaped beam (VSB) with the deflector. Most VSB systems utilize multi stage deflection architecture to obtain a high precision and a high-speed deflection at the same time. Many companies use the VSB mask writer and
they have a lot of experiences about Image Placement (IP) error suffering from contaminated EOS deflector. And also most of VSB mask writer users are having already this error. In order to use old VSB mask writer, we introduce the method how to compensate unexpected IP error from VSB mask writer. There are two methods to improve this error due to contaminated deflector. The one is the usage of 2nd stage grid correction in addition to the original stage grid. And the other is the usage of uncontaminated area in the deflector. According to the results of this paper, 30% of IP error can be reduced by 2nd stage grid correction and the change of deflection area in deflector. It is the effective method to reduce the deflector error at the VSB mask writer. And it can be the one of the solution for the long-term production of photomask.
The availability of defect-free masks remains one of the key challenges for inserting extreme ultraviolet lithography
(EUVL) into high volume manufacturing. Recently both blank suppliers achieved 1-digit number of defects at 60nm in
size using their M1350s. In this paper, a full field EUV mask with Teron 61X blank inspection is fabricated to see the
printability of various defects on the blank using NXE 3100. Minimum printable blank defect size is 23nm in SEVD
using real blank defect. Current defect level on blank with Teron 61X Phasur has been up to 70 in 132 X 132mm<sup>2</sup>. More
defect reduction as well as advanced blank inspection tools to capture all printable defects should be prepared for HVM.
3.6X reduction of blank defects per year is required to achieve the requirement of HVM in the application of memory
device with EUVL. Furthermore, blank defect mitigation and compensational repair techniques during mask process
needs to be developed to achieve printable defect free on the wafer.
As design rule has decreased, blank type or photo resist, which meets requirement of resolution, has been developed.
HT PSM mainly used to pattern small line width has no longer advantages for immersion wafer process. It makes binary
mask to be gradually used for mask production. Comparing to HT PSM, the production of binary mask has a relatively
simple process. However, we may consider optical density, PR or Cr thickness, etch selectivity, and ID bias related to
linearity for applying binary mask below sub-45nm. In this paper, we will compare and analyze difference between
actual manufacture and theoretical optic level such as optical density. Finally, based on our experiment, optimal
combination of photoresists and blanks which can realize sub-45nm node will be discussed.
In the photo-lithography process, a mask is one of the most important items because CD error from its imperfection is
transferred to the CD error on the wafer. And the CD error amplification from the mask CD to the wafer CD is denoted
by Mask Error Enhancement Factor (MEEF).
As the device shrinks so fast, MEEF increases conspicuously and massive OPC is necessary to secure the target
pattern CD and the proper process margin on the wafer. Therefore the mask CD uniformity and the just mean-to-target
(MTT) are very important to minimize the CD variation on the wafer level.
In most cases, MTT and CD uniformity for a certain device are not defined exactly. What we know is that the smaller,
the better. Because just small value of MTT and CD uniformity is not the reasonable guideline for the mask fabrication
and inducing high mask cost, defining the logical MTT and CD uniformity prospect for a certain device or layer is very
As the necessity of the low k<sub>1</sub> process increases, MTT and CD uniformity specifications become tighter and tighter.
However the proper mask specification for sub-65nm real device has not been defined yet and not been studied
considering the mask fabrication and MEEF.
In this study, MTT and CD uniformity specification of the sub-65nm real device patterns are discussed with respect to
the mask pattern linearity and MEEFs. Mask linearity is one of the typical items for the mask fabrication and strongly
related to MTT and CD uniformity. MTT and CD uniformity tolerance also follows OPC tolerance, and OPC tolerance is
directly related to the pattern layouts and MEEF. To define the mask specification for the sub-65nm device, an example
of mask linearity effect is shown; MEEFs of the critical pattern designs are calculated and compared with each other;
MTT, CD uniformity and MEEF relationship is commented.
With decreasing the design node, there are some candidates for the optical lithography technology. Double Exposure
Technology (DET) is the one of the solution to extend the resolution limit down to k1 less than 0.25 for the next
generation devices. To accomplish DET, photomask MTT, CD uniformity, and the overlay between the layers for the
dual exposure are important as the photomask process aspect.
MTT and CD uniformity have been frequently discussed for Single Exposure Technology (SET), but the overlay and
the registration have not been discussed yet with the view of DET. In this work, the feasibility of mask fabrication,
especially the overlay and the registration for DET are analyzed. The current mask limit of DET is discussed
considering MTT, uniformity, and overlay.
For the half pitch below 45nm, the required sub-resolution feature size is about to be 60nm, and the uniformity of dense
lines to be below 3.4nm for the mask fabrication. To achieve this requirement, the reduction of beam blur is necessary.
On the mask patterning using 50keV electron beam, the beam blurring due to coulomb interaction and resist
characteristics is the main effect of the pattern image degradation and the limit of CD uniformity.
In this report, we present the effect of the beam blur induced by coulomb interaction and resist. And we report the recent
simulated and experimental results on the resolution change depending on bream blur and design node. Finally, we
conclude that the reduction of beam blur can improve the mask quality and there is a compatible condition between the
beam blur and the mask fabrication.