Directed self-assembly (DSA) of block copolymers (BCP) has attracted significant interest as a patterning technique over the past few years. We have previously reported the development of a new process flow, the CHIPS flow (Chemo-epitaxy Induced by Pillar Structures), where we use ArFi lithography and plasma etch to print guiding pillar patterns for the DSA of cylindrical phase BCPs into dense hexagonal hole arrays of 22.5 nm half-pitch and 15 nm half-pitch . The ability of this DSA process to generate dense regular patterns makes it an excellent candidate for patterning memory devices. Thus, in this paper we study the applicability of the CHIPS flow to patterning for DRAM storage layers. We report the impact of various process conditions on defect density, defect types and pattern variability. We also perform detailed analysis of the DSA patterns, quantify pattern placement accuracy and demonstrate a route towards excellent LCDU after pattern transfer into a hard mask layer.
Spacer multi patterning process continues to be a key enabler of future design shrinks in DRAM and NAND process flows. Improving Critical Dimension Uniformity (CDU) for main features remains high priority for multi patterning technology and requires improved metrology and control solutions.<p> </p> In this paper Spacer Patterning Technology is evaluated using an angle resolved scatterometry tool for both intra field control of the core CD after partition etch (S1) and interfield pitch-walking control after final etch (S1-S2). The intrafield measurements were done directly on device using dense sampling. The inter-field corrections were based on sparse full wafer measurements on biased OCD targets. The CDU improvement after partition-etch was verified by direct scatterometer and CD-SEM measurement on device. The final etch performance across wafer was verified with scatterometer on OCD target. <p> </p>The scatterometer metrology in combination with the control strategy demonstrated a consistent CDU improvement of core (S1) intrafield CD after partition etch between 23-39% and 47-53% on interfield pitch-walking (S1-S2) after final etch. To confirm these improvements with CD-SEM, oversampling of more than 16 times is needed compared to scatterometer. <p> </p>Based on the results it is concluded that scatterometry in combination with the evaluated metrology and control strategy in principle qualifies for a spacer process CDU control loop in a manufacturing environment.
Aggressive advancements in semiconductor technology have resulted in integrated chip (IC) manufacturing capability at sub-20nm half-pitch nodes. With this, lithography overlay error budgets are becoming increasingly stringent. The delay in EUV lithography readiness for high volume manufacturing (HVM) and the need for multiple-patterning lithography with 193i technology has further amplified the overlay issue. Thus there exists a need for technologies that can improve overlay errors in HVM. The traditional method for reducing overlay errors predominantly focused on improving lithography scanner printability performance. However, processes outside of the lithography sector known as processinduced overlay errors can contribute significantly to the total overlay at the current requirements. Monitoring and characterizing process-induced overlay has become critical for advanced node patterning. Recently a relatively new technique for overlay control that uses high-resolution wafer geometry measurements has gained significance. In this work we present the implementation of this technique in an IC fabrication environment to monitor wafer geometry changes induced across several points in the process flow, of multiple product layers with critical overlay performance requirement. Several production wafer lots were measured and analyzed on a patterned wafer geometry tool. Changes induced in wafer geometry as a result of wafer processing were related to down-stream overlay error contribution using the analytical in-plane distortion (IPD) calculation model. Through this segmentation, process steps that are major contributors to down-stream overlay were identified. Subsequent process optimization was then isolated to those process steps where maximum benefit might be realized. Root-cause for the within-wafer, wafer-to-wafer, tool-to-tool, and station-to-station variations observed were further investigated using local shape curvature changes – which is directly related to stresses induced by wafer processing. In multiple instances it was possible to adjust process parameters such as gas flow rate, machine power, etc., and reduce non-uniform stresses in the wafer. Estimates of process-induced overlay errors were also used to perform feedforward overlay corrections for 3D-NAND production wafers. Results from the studies performed in an advanced semiconductor fabrication line are reported in this paper.
For several decades, the semiconductor industry has been controlling site flatness of the starting wafer material by defining tight specs on industry-standard site flatness metrics such as SFQR (Site Frontsurface-referenced least sQuares/Range) and ESFQR (Edge Site Frontsurface-referenced least sQuares/Range) that scale with technology nodes. The need for controlling site flatness of the starting material stems from previous research that shows that site flatness directly impacts lithography defocus. The wafer flatness variation changes significantly due to wafer processing downstream such as CMP, etch, and film deposition. Hence, for 2X nm and smaller technology nodes with very stringent focus process windows, it is critical to control wafer flatness variations at critical steps along the semiconductor process flow. In this paper, the capability of an interferometer-based patterned wafer metrology tool to predict lithography defocus is validated by comparison to scanner leveling data. The patterned wafer metrology tool is used to characterize the impact of near-edge flatness changes on the critical dimension (CD) of the contact holes due to different edge CMP process conditions. The results of the characterization illustrate how a site flatness specification or threshold can be developed for critical patterning steps. The paper also illustrates how the patterned wafer metrology tool can be used to identify processes causing site flatness variations. Finally, the site flatness variation at these processes can be monitored using the pattern wafer metrology tool to detect process drifts and excursion before patterning.
ASML NXE3100 has been introduced for EUV Pre-Production, and ASML NXE3300 for High Volume Manufacturing will be installed from this year. EUV mask defect control is the one of the concerns for introducing EUVL to device manufacturing, for current EUV mask defect level is too high to accept for device volume production. EUV mask defects
come from mask blank, mask process and mask handling. To have reduced mask defect level, quality control of blank
mask, optimization of EUV mask process and improvement of EUV mask handling need to be ready. In this paper, we analyze printed defects exposed from EUV full field mask at NXE3100. For this analysis we trace mask defects from mask to wafer printing. From this we will show current EUV mask’s defect type and numbers. Acceptable defect type, size and numbers for device manufacturing with EUVL will be shown. Through investigating printing result of natural ML defects, realistic level of natural ML defects will be shown.
Improving Critical Dimension Uniformity (CDU) for spacer double patterning features is a high priority for double
patterning technology. In spacer double patterning the gaps between the spacers are established through various
processes (litho, etch, deposition) with different process fingerprints and the CDU improvement of these gaps requires an
improved control solution. Such a control solution is built upon two pillars: metrology and a control strategy.
In this paper Spacer Patterning Technology CDU control using an angle resolved scatterometry tool is evaluated. CD
results obtained with this scatterometer on CDU wafers are measured and the results are correlated with those from the
traditional CD-SEM. CD wafer fingerprints are compared before and after applying the advanced control strategy and
CDU improvements are reported. Based on the results it is concluded that scatterometry qualifies for a spacer process
CDU control loop in a manufacturing environment.
Intra-field CD uniformity control is one of hurdles in EUV lithography. Reflection imaging system intrinsic to EUV
causes CD non-uniformity especially in exposure field edge. To analyze dominant contributors to make this intra-field
CD non-uniformity in EUV lithography, influence of flare from adjacent fields and in-band and out of band refection
from reticle masking blind(REMA) and mask black border were investigated through intensive sampling of CD
measurement. Also mask border condition and REMA open settings are split into various settings to find out the impacts
from each contributor. Two ASML EUV scanners, alpha demo tool(ADT) and pre-production tool(PPT) are used for the
experiment. Fortunately, DUV out of band(OoB), reflection of REMA and the flare from adjacent fields are found to be
not significant in NXE3100. The results presented here lead us to the conclusion that the EUV refection from mask black
border is the main contributor and CD non-uniformity of the field edge can be overcome through optimized REMA
Typical overlay metrology marks like Box-in-Box or Advanced-Imaging-Marks print surprisingly poor when exposed
with extreme off-axis-illumination. This paper analyzes the root-cause for this behavior and establishes a method how to
understand and predict the results of overlay metrology on resist. A simulation flow is presented which covers the
lithographic exposure as well as the actual inspection of the resist profiles. This flow is then used to study the impact of
scanner/process imperfections on the overlay measurements; both image-based and diffraction-based overlay metrology
are covered. This helps to gain a deeper understanding of the critical parameters in the printing and inspection of overlay
marks, and eventually develop and assess mark enhancement strategies for image-based overlay metrology such as
chopping, or assess the benefit of diffraction-based overlay metrology. In parallel to the simulations, results of wafer
exposures are presented which investigate various aspects of overlay metrology and validate our simulations.
Overlay performance will be increasingly important for Spacer Patterning Technology (SPT) and Double Patterning
Technology (DPT) as various Resolution Enhancement Techniques are employed to extend the resolution limits of
lithography. Continuous shrinkage of devices makes overlay accuracy one of the most critical issues while overlay
performance is completely dependent on exposure tool.
Image Based Overlay (IBO) has been used as the mainstream metrology for overlay by the main memory IC companies,
but IBO is not suitable for some critical layers due to the poor Tool Induced Shift (TIS) values. Hence new overlay
metrology is required to improve the overlay measurement accuracy. Diffraction Based Overlay (DBO) is regarded to
be an alternative metrology to IBO for more accurate measurements and reduction of reading errors. Good overlay
performances of DBO have been reported in many articles. However applying DBO for SPT and DPT layers poses
extra challenges for target design. New vernier designs are considered for different DPT and SPT schemes to meet
overlay target in DBO system.
In this paper, we optimize the design of the DBO target and the performance of DBO to meet the overlay specification
of sub-3x nm devices which are using SPT and DPT processes. We show that the appropriate vernier design yields
excellent overlay performance in residual and TIS. The paper also demonstrated the effects of vernier structure on
overlay accuracy from SEM analysis.