Post exposure bake (PEB) is the most important process for chemically amplified resist to make nano-scale device.
According to 2007 ITRS roadmap, critical dimension (CD) should be controlled below 1.9 nm on sub-22 nm half
pitch in whole process of semiconductor. But CD error can be happened during the whole processes of exposure,
PEB, develop, and etching. For this study, we assumed PEB process is just one of four processes, so that we take
arithmetic mean error of four process, namely, ~ 0.5 nm (1.9 nm / 4) CD error should be controlled during PEB,
even though PEB is the critical processes for CD control. 1 degree PEB temperature difference would make 3 nm
CD change, so that we should control the temperature variation below 0.2 degree to control CD variation within 0.5
nm for 22 nm node. However, temperatures on the whole hot plate is not perfectly uniform. The temperature at the
heat source is higher than that at the position with no heat source. Such a temperature difference inside hot plate
would be directly transferred to the wafer and eventually inside the photoresist. Thus the temperature distribution
inside the whole photoresist would be non-uniform, and this would make non-uniform CD distribution eventually.
We calculated the temperature distribution within the hot plate in accordance with the position and structure of heat
source. We also calculated the temperature distribution inside photoresist by considering the heat conduction. In
addition to that, we estimated the possible CD variation caused by the non-uniform temperature distribution within
photoresist on wafer.
Contact hole (CH) patterning, specially for sub-50 nm node, is one of the most difficult technique in optical
lithography. Resist reflow process (RRP) can be used to obtain smaller CH. RRP is a simple technique that the
resist, after the develop process, is baked above the glass transition temperature (Tg). Heating causes the resist flowing, and we can obtain smaller dimension of CHs. However, RRP is unmanageable method because CH
offset caused by pattern position in random array CH. So we tried OPC to find uniform CD for every CH, and
we could obtain the uniform CD for every CH after RRP. However, we still have CH position shift problem.
Because of a difference in an amount of resist that flow into the hole in random array during the reflow process,
position shift occurs. This position shift makes overlay error, and it may exceed the overlay error limit suggested
by ITRS roadmap. In this work, we try to find not only uniform CD size of each CH, but also optimum
condition for correcting CH position shift by using home-made simulation. Moreover, we confirmed the
tendency of CH position shift by e-beam lithography experiment. Consequently, we confirmed that CH moved
to receding direction from each other, and obtained sub-50nm CHs in random array by considering the position
shift through the simulation and experiment.
Extreme ultra-violet lithography (EUVL) has been prepared for next generation lithography for several years.
We could get sub-22 nm line and space (L/S) pattern using EUVL, but there are still some problems such as
roughness, sensitivity, and resolution. According to 2007 ITRS roadmap, line edge roughness (LER) has to be
below 1.9 nm to get a 22 nm node, but it is too difficult to control line width roughness (LWR) because line
width is determined by not only the post exposure bake (PEB) time, temperature and acid diffusion length, but
also the component and size of the resist. A new method is suggested to reduce the roughness. The surface
roughness can be smoothed by applying the resist reflow process (RRP) for the developed resist. We made resist
profile which has surface roughness by applying exposure, PEB and development process for line and space
pattern. The surface roughness is calculated by changing parameters such as the protected ratio of resin. The
PEB time is also varied. We compared difference between 1:1 L/S and 1:3 L/S pattern for 22 nm. Developed
resist baked above the glass transition temperature will flow and the surface will be smoothed. As a result, LER
and LWR will be much smaller after RRP. The result shows that the decreasing ratio of LER due to RRP is
larger when initial LER is large. We believe that current ~ 5 nm LWR can be smoothed to ~ 1 nm by using RRP
According to the ITRS roadmap, DRAM half pitch (hp) will reach to 32 and 20 nm in 2012 and 2017
respectively. However, it is difficult to make sub-40 nm node by single exposure technology with currently
available 1.35 numerical aperture (NA) ArF immersion lithography. Although it is expected to enable 32 nm hp
with either double patterning technology or extreme ultra-violet lithography, there are many problems to be
solved with cost reduction. Thus, the study of high-index fluid immersion technology should be pursued
simultaneously. ArF water immersion systems with 1.35 NA have already introduced for 40 nm hp production.
ArF immersion lithography using high-index materials is being researched for the next generation lithography.
Currently, many studies are undergoing in order to increase NA with higher index fluid and lens in immersion
technology. The combination of LuAG (n=2.14) and third-generation fluid could be used to make 1.55 NA. This
combination with 0.25 k1, 32 nm hp can be obtained by single exposure technology. In order to check the
realization of this process and to check the possible process hurdles for this high NA single exposure technology,
32 nm hp with 1:1 line and space patterning is tried. Various illumination conditions are tried to make 1:1 32 nm
hp and the exposure and develop conditions are varied to check whether this single exposure can give
processible window. As a result, 32 nm hp can be obtained by single exposure technology with 1.55 NA.
According to ITRS road map, it will be achieved 22 nm half pitch until 2016. However, it is hard to make although EUV, high index immersion. We have positive strategy for 22 nm half pitch with immersion and double patterning and RRP. We can make 22 nm half-pitch with hard mask by using RRP that can shrink trench pattern and double patterning that can get over resolution limitation. Immersion technology can make 44 nm half pitch in NA 1.35. When the developed resist profile can be reflow, so line is increased and space is decreased. It can be 22 nm trench pattern with 66 nm width by using RRP. Hence, we can obtain 66 nm line and 22nm space pattern by etching. And then, we can obtain 22 nm half pitch after doing double patterning. We tried to evaluate this strategy by commercial and home-made simulator.
In order to shrink down the contact hole which is usually much larger than other patterns, the resist reflow process (RRP)
has been widely used. Various types, shapes, and pitches of contact hole arrays are made by RRP, but RRP was limited to
be used only for contact hole patterns. The same RRP method is expanded to 32 nm node arbitrary and complex patterns
including dense line and space patterns. There might be simple 1-dimensional patterns, but 2-dimensional proximity
conflict patterns are difficult to make in general. Specially, the data split with proximity correction needs a lot of
attention for double patterning. 32 nm node arbitrary patterns can be easily made by using RRP without complex data
Making a sub-32 nm line and space pattern is the most important issue in semiconductor process. Specially, it
is important to make line and space pattern when the device type is NAND flash memory because the unit cell is mostly
composed of line and space pattern. Double patterning method is regarded as the most promising technology for sub-32
nm half-pitch node. However, double patterning method is expensive for the production and heavy data split is required.
In order to make cheaper and easier patterning, we suggest a resist reflow process (RRP) method for 32 nm 1:1 line and
space pattern. It is easier to make 1:3 pitch than 1:1 pitch line and space in terms of aerial image, and RRP can make 1:3
pitch aerial image to 1:1 resist image. We used home-made RRP simulation based on Navier-Stokes equation including
surface tension effect. Solid-E is used for optical simulation, and e-beam lithography is used for the experiment to check
50 nm random contact hole array by resist reflow process (RRP) was studied to make 32 nm node device. Patterning
of smaller contact hole array is harder than patterning the line and space. RRP has a lot of advantages, but RRP strongly
depends on pattern array, pitch, and shape. Thus, we must have full knowledge for pattern dependency after RRP, and
then we need to have optimum optical proximity corrected mask including RRP to compensate the pattern dependency in
To make optimum optical proximity and RRP corrected mask, we must have better understanding that how much resist
flows and where the contact hole locations are after RRP. A simulation is made to correctly predict RRP result by
including the RRP parameters such as viscosity, adhesion force, surface tension and location of the contact hole. As a
result, we made uniform 50 nm contact hole patterns even for the random contact hole array and for different shaped
contact hole array by optical proximity corrected RRP.
Making a sub-100 nm contact hole pattern is one of the difficult issues in semiconductor process. Compared with
another fabrication process, resist reflow process is a good method to obtain very high resolution contact hole. However
it is not easy to predict the actual reflow result by simulation because very complex physics and/or chemistry are
involved in resist reflow process. We must know accurate physical and chemical constant values and many fabrication
variables for better prediction. We made resist reflow simulation tool to predict approximate resist reflow as functions of
pitch, temperature, time, array, and so on. We were able to see the simulated top view, side view and the changed hole
size. We used Navier-Stokes equation for resist reflow. We had varied the reflow time, temperature, surface tension, and
3-dimensional volume effect for old model. However the photoresist adhesion is another very important factor that was
not included in the old model. So the adhesion effect was added on Navier-Stokes equation and found that there was a
distinctive difference in reflowed resist profile and the contact hole width compared to the case of no adhesion effect.