For the past years, ArF immersion has been employed as the major lithography tool in the foundry manufacturing to fabricate the patterns of minimum pitch and size. However, for semiconductor scaling beyond N7 the application of EUV lithography is considered to be crucially important to overcome the physical limitation of ArF immersion and to realize even smaller patterns. In the case of ArF photo processes, the best mask size for a specific pitch could be selected with the consideration of optical performances such as NILS, MEEF, etc. In contrast, for the EUV processes the optical and resist stochastic effect should also be taken into account as an important factor in deciding the best mask size. In this paper, we are going to discuss the dose and mask size optimization process for an DRAM contact hole layer with EUV lithography utilizing stochastic simulations; this contains also the stochastic response of the resist. In order to calibrate a predictive stochastic resist model, which is required for this application, measurements of the stochastic resist response are necessary. In addition, the systematic and stochastic errors of CD-SEM measurements have to be estimated. We will compare experimentally obtained NILS and MEEF to simulated results, which are in very good agreement. Also, we show a comparison of experimental and computational analysis of LCDU (Local CD Uniformity).
In multi patterning processes, overlay is now entangled with CD including OPC and stochastics. This combined effect is a serious challenge for continued shrink and is driving down the allowed overlay margin to an unprecedented level. We need to do everything to improve overlay where accurate measurement and control of wafer deformation is extremely important. This requires accuracy in overlay metrology that decouples target asymmetry from wafer deformation. Multiwavelength diffraction-based overlay (DBO) is positioned for providing such accuracy while maintaining the required measurement speed. At the same time, with the increase of process complexity in advanced nodes, several new types of target asymmetries are introduced. Some of such asymmetries vary even within the target / grating area (intra-grating) and some are so severe that it impacts the center of gravity shift of the overlay target.
In order to meet the tightened lithography performance requirement for EUV systems, a good on-product focus control with accurate metrology is essential. In this manuscript we report on a novel metrology solution for the EUV on-product focus measurement using YieldStar. The new metrology has been qualified on the Logic product wafers and when combined with the advanced techniques and algorithm shows a performance that is accurate and precise enough to meet EUV requirements. Furthermore, the new methodology provides the opportunity for on-product focus monitoring and control through different scanner interfaces. Here we present a case in which the Imaging Optimizer using the EUV metrology data shows an improvement of over 20% on the focus uniformity.
In leading edge patterning processes, overlay is now entangled with CD including OPC residuals and stochastics. This combined effect is a serious challenge for continued shrink and can be characterized with an Edge Placement Error (EPE) budget containing multi-domain components: global and local CD, local placement errors, overlay errors, etch biases and OPC. EPE defines process capability and ultimately relates to device yield. Understanding the EPE budget leads to efficient ways to monitor process capability and optimize it using EPE based process control applications. We examine a critical EPE use case on a leading edge DRAM node. We start by constructing and verifying the EPE Budget via densely sampled on-product in-device local, global CD and Overlay metrology after the etch process step. EPE budget contributors are ranked according to their impact to overall EPE performance and later with simulated EPE performance improvements per component. A cost/benefit analysis is shown to help choose the most HVM-friendly solutions.
Utilizing a unique high NA optical system, a new methodology to measure device overlay accurately has been developed with a key differentiation. Historically, optical techniques to measure features below the image resolution require supporting measurement techniques to be used as a reference to anchor the optical measurement. This novel selfreference methodology enables accurate and robust optical metrology for device features after etch eliminating the need for external reference measurements such as Decap, x-sections or high landing energy SEMs. In this paper, we discuss how a high NA Optical Metrology system enables measurements on small area device replica targets, which enables the ability to create a reference target for device measurements. The methodology utilizes this reference target to enable accurate direct on device overlay measurements without the need for an external reference. Furthermore, the technique is expanded to improve the robustness of the measurement and monitor live in production the health of the recipe, ensuring accuracy overtime. This ultimately leads to a method to extend the recipes in real-time based on the health KPIs. The improved accurate and robust device overlay measurements have proven to improve the overlay performance compared to other techniques. This, combined with the speed of optical systems, enables unconstrained dense measurements directly on device structures after etch, allowing for improved overlay control.
With the increase of litho-etch steps the industry requires metrology to deliver solutions to improve throughput of overlay measurements without impacting accuracy. ASML’s YieldStar 350E is capable of utilizing targets, which can measure the overlay of multiple layers simultaneously. For the work discussed in this paper, an evaluation is performed on Logic product wafers using both single-layer and multi-layer (MLT) quad type targets (able to capture up to four litho-etch steps). Different target types were compared in terms of Move-and-Acquire (MA) time, residual and matching to SEM. Using the MLT targets, an MA time improvement of 56% was demonstrated on the singlelayer. The maximum delta between the overlay residual among the YieldStar targets after applying an high order model was shown to be 0.05 nm. In comparison to after-etch overlay, the correlation of the MLT target was determined with an R2 >; 0.95 using a set-get wafer with induced 10 nm overlay range. On a normal production wafer, the correlation was R2 > 0.67, which is high on a wafer without induced overlay. The comparison of modeling parameters between SEM and MLT targets shows a good match (< 0.16nm) as well.
As critical dimensions for advanced two dimensional (2D) DUV patterning continue to shrink, the exact process window becomes increasingly difficult to determine. The defect size criteria shrink with the patterning critical dimensions and are well below the resolution of current optical inspection tools. As a result, it is more challenging for traditional bright field inspection tools to accurately discover the hotspots that define the process window. In this study, we use a novel computational inspection method to identify the depth-of-focus limiting features of a 10 nm node mask with 2D metal structures (single exposure) and compare the results to those obtained with a traditional process windows qualification (PWQ) method based on utilizing a focus modulated wafer and bright field inspection (BFI) to detect hotspot defects. The method is extended to litho-etch litho-etch (LELE) on a different test vehicle to show that overlay related bridging hotspots also can be identified.
To a major candidate and beyond, directed self-assembly (DSA) lithography is investigated on DRAM contact-hole fabrication. We perform a systematic study about behavior of asymmetric PS-b-PMMA block copolymers (BCP) within pillar confinement for DSA and find that selectively removed PMMA contact domain has a different morphology according to chemically modified pillar surfaces. We calculate the perturbation of PMMA contacts by pillar diameter using free energy magnitude model. This established model provides practical engineering insight for present pillar scheme and future graphoepitaxial self-assembly techniques for semiconductor DSA procedure.
In this study, overall critical dimension (CD) error budget analysis procedure is proposed to estimate the source of CD
error. Until now, local CD variation has been treated as noise or uncertainty, since it has been considered not real, and it
is difficult to be measured. However, the actual measurement result shows the local CD variation occupies a significant
portion of overall CD variation. We included the local variation into overall CD budget analysis, and performed the
budget break-down of the local CD variation. This analysis was performed on the layers of a sub-50nm DRAM device.
We calculated local CD uniformity from CD SEM measurement data having multi-point measurement on each frame.
Metrology error of wafer CD SEM and mask CD SEM was measured, and local CD uniformity (CDU) of mask was also
measured. To estimate the impact from the mask local CDU, we performed simulation with a virtual mask shape which
has the same level of local variation with real mask. The remaining budget, except metrology and mask induced budget,
is treated as a process roughness. To predict the budget caused by process roughness, a randomly varying threshold map
was applied. In this approach, the local CD variation of 2-dimensional patterns is considered as an extension of the LWR
In this paper, two different methods of double exposure are proposed to improve the resolution in low k1 lithography. One is using an additional mask to complement the lack of image contrast. The other is to fix the mask and only use combinations of illumination systems to increase image contrast. By applying image assisting double exposure to asymmetry dense contact under k1=0.33, the process window can be doubled in comparison to the single exposure method. By an appropriate design of two masks, we could also minimize the image distortion from overlay shift by mixture of masks. Effective first order efficiency is defined as a new term in double exposure with complementary illumination. The larger the value is, the better the image contrast becomes. Through an experiment and simulation in k1=0.30, in double exposure with two illuminations and the same mask, that wider process window was obtained than in single exposure with optimized illumination system, and also 0.10um of DOF (Depth of Focus) was obtained under k1=0.28.
Recently, the design rule shrinkage of DRAM devices has been accelerated. According to International Technology Roadmap for Semiconductor (ITRS) 2001, 90 nm node will start in 2004. For this achievement, lithography has been standing especially in the forefront and leading the ultra fine patterning technologies in the manufacturing of semiconductor devices. We are now in the moment of transition from the stronghold of KrF to the prospective of ArF. In this paper, we applied ArF process to the real DRAM devices of 90nm node. We proved good pattern fidelity and device performance. The ArF process, however, has still some weak points - resist shrinkage and LER (Line Edge Roughness). Resist shrinkage is very crucial problem for measuring CD. To overcome it, we applied ASC (Anti-Shrinkage Coating) process to ArF resist and improved the CD measurement. LER also becomes an issue, as the design rule is shrink. It is found that they are very dependent on resist type. However, it could be cured effectively by VUV treatment. Finally we will mention the current status of low k1 factor and the future lithographic strategy of which technologies will be most feasible based on current situation.
Process windows, MEEF (Mask Error Enhancement Factor), flare, aberration effect of the CLM (Cr-less PSM) were measured by the simulations and experiments for the various DRAM cell patterns compared with 6% transmittance HTPSM in the ArF lithography. We designed CLM layouts of sub 100nm node DRAM cells concerning the mask manufacturability, maximizing the NILS (Normalized Image Log Slope) and minimizing the MEEF with a semi-automatic OPC tool. Isolation, line and space and various contact patterns showed increasing process windows compared with HTPSM and this strongly depended on the layout design. Using 0.75 NA ArF Scanner, CLM showed NILS reduction by about 10% in the presence of lens aberration and flare, which reduced DoF margin by about 0.1~0.2 μm depending on the layer. So the critical layers in sub 100 nm node DRAM satisified 10% of EL (Exposure Latitude) and 0.4 μm of DoF (Depth of Focus) margin.
For 100nm-level patterning using optical lithography, high NA system and various RETs such as PSM, off-axis illumination and OPC are obviously required. In particular, assistant feature (AF)-OPC is indispensable to overcome narrow depth of focus (DOF) caused by iso-dense bias and to compensate for linearity difference under the given OAI condition. Previously we reported the application of AF-OPC in DRAM process with 120nm design rule. The extraction of OPC rule and the feasibility of AF-OPC were successfully confirmed by experimental method in real process. In this paper, more comprehensive and aggressive AF-OPC rule is investigated. The old rule is modified in order to obtain larger common DOF. TO avoid dead zone that means discontinuity between dense line and semi-dense line, we apply a comprehensive rule such as insertion of AF between the neighboring main patterns as many as possible. As a result, the discontinuity of OPC application, which is used with or without AF in the boundary region, is effectively minimized. Also, polygon-shaped AF is used to improve DOF of special main pattern. And then, the mask specification and the behavior of isolated line pattern are predicted in case of very high NA KrF and ArF lithography by simulation result. Considering 100nm design rule, the decrease of common DOF is expected to be severer than now. Finally, the optimum AF-OPC rules such as AF size, space and shape are available and shown in case of very high NA KrF and ArF lithography.
We studied lithography process of 0.31 k1 for DRAM device with KrF light source. DRAM device with 100 nm half-pitch design rule, which can facilitate 4 Giga-bit in a chip, can be patterned with the aid of super resolution enhancement techniques (SRET) and high NA (equals0.7) KrF scanner. The SRET includes the use of strong off-axis illumination (OAI) and attenuated phase shift mask (8% transmittance). In the case of using the SRET, those of very large iso-dense (I-D) bias from the optical proximity effect (OPE), narrow depth of focus (DOF) of (semi-) isolated features and existence of dead-zone in the peripheral circuit and so forth, are emerging as critical issues to be solved except the very fundamental lens aberration. These problems can only be solved when aggressive optical proximity correction (OPC) techniques such as selective bias and assistant feature to (semi-) isolated features are used for every critical layer of the device, where the OPC rules were generated from simulations and empirical experiments. Besides OPC techniques, close and cooperative approach of lithographers and designers is also necessary for the process oriented layout design especially to avoid the dead-zone that SRET generates. We have tried to customize the lithography process design for 0.31 k1 and finally obtained the common process latitude to make the full 4 Giga-bit DRAM device lithography feasible on this basis.
The extension of optical lithography to sub-0.18micrometers design rule using high NA KrF lithographic tool and resolution enhancement technique (RET) is strongly required because of the delayed ArF lithography technology. The theoretical limits, i.e., the diffraction limits of KrF lithography show that 0.1(Mu) m is in the unreachable region with current exposing tool of 0.6NA and even with high NA KrF scanners which will be available soon. Therefore 0.13micrometers device with 0.26micrometers pitch will be a real challenge to most lithographers. In this paper we discuss the status of 0.13micrometers device and show some of the critical device patterns exposed with several KrF scanners which are currently available. Many problems can easily be predicted and must be overcome. The challenge, however, seems to be surmountable in the near future.