This paper presents a stochastic theory for the interpretation of photon counting histograms in fluorescence fluctuation spectroscopy (FFS). New concepts of an effective volume and a single molecule probability distribution are introduced to characterize a molecular species. Whereas the effective volume corresponds to the visibility of a molecular species in a given confocal setup, the single molecule probability distribution gives the signal measured for a single visible molecule. Specific properties of the effective volume and the single molecule probability distribution are discussed. Advantages arise for the high precision measurements of concentrations, mixtures, and binding constants especially for complex molecular environment, e.g. in flow systems and cell compartments.
In this paper we present a novel highly sensitive detection system for diagnostic applications. The system is designed to
meet the needs of medical diagnostics for reliable measurements of pathogens and biomarkers in the low concentration
regime. It consists of a confocal detection unit, micro-structured sampling cells, and a "Virtual lab" analysis software.
The detection unit works with laser induced fluorescence and is designed to provide accurate and highly sensitive
measurement at the single molecule level. Various sampling cells are micro-structured in glass, silicon or polymers to
enable measurements under flow and nonflow conditions. Sampling volume is below one microliter. The "Virtual lab"
software analyzes the light intensity online according to the patent pending "Accurate Stochastic Fluorescence
Spectroscopy" (ASFS) developed by FluIT Biosystems GmbH. Tools for simulation and experiment optimization are
included as well. Experimental results for various applications with relevance for in vitro diagnostics will be presented.
Due to economical reasons junction isolated CMOS should be extensively exploited for temperature resistant electronics. A limitation at high temperatures is given by parasitic effects in the substrate, namely leakage currents, latch-up, and snap-back. Snap-back is caused by the parasitic bipolar action of single MOS transistor structures. We have investigated the temperature dependence of the snap-back phenomenon up to 250 degree(s)C using silicided LDD-MOS transistors with gate lengths of 0.8 micrometers and 1.0 micrometers as test devices. Measurements were performed dynamically with short pulses of rectangular shape. The snap-back breakdown voltage of 0.8 micrometers NMOS transistors decreases from 14.3 V at room temperature to 10.6 V at 250 degree(s)C and the triggering voltage for second breakdown from approximately 9.4 V at RT to 6.2 V at 250 degree(s)C. For PMOS transistors no snap-back was observed up to 20 V pulse height. The results show that snap-back is not a problem for this CMOS process up to the specified power supply voltage of 5 V. To consider shrinking effects were performed 2-dim FEM simulations. At high temperatures, the breakdown voltage is reduced with increasing temperature and decreasing gate length. This correlates to a value of the current gain of the parasitic bipolar transistor (beta) > 1 at the breakdown point. The commonly applied measures for designing processes with shorter gate lengths, like e.g. higher tub doping, are also sufficient to avoid snap-back under bias conditions even at temperatures up to 250 degree(s)C.
There is an increasing demand from automotive, aircraft and space industry for reliable high temperature resistant electronics. Circuits with reliable functionality up to temperatures of 250 degree(s)C would be sufficient for most of these applications. Digital standard cells and operational amplifiers are the basic building blocks of these circuits. Commercially available digital standard cell libraries and operational amplifiers are normally specified for operation up to a maximum temperature of 125 degree(s)C. Hence, the purpose of this work was the design and characterization of digital standard cells and operational amplifiers for operation up to 250 degree(s)C using a low-cost 1.0 micrometers epi-CMOS process. Several design measures were applied to the cells in order to further improve latch-up resistivity and to limit leakage currents, respectively. The transfer curves of all digital cells for all input signal combinations have been recorded in the temperature range from 30 to 250 degree(s)C. Significant results are very low temperature shifts of the noise margins and of the switching point, respectively. Furthermore, the low (0 V) and high (5 V) levels are reached exactly over the entire temperature range. Outstanding characteristics of the operational amplifier comprise low open-loop gain temperature drift as well as low offset and offset temperature drift, respectively. The open-loop gain was greater than 83 dB at room temperature with a drift of less than 0.02 dB/ degree(s)C. The offset voltage amounted to -1 mV at room temperature and 1 mV at 250 degree(s)C, respectively. The long-term behavior of these cells is currently under investigation.
The purpose of this work was to investigate the latch-up temperature dependence of majority carrier guard structures with the goal to find design rules for latch-up free high temperature operation of a CMOS- ASIC. Measurements up to 250 degree(s)C show an enhanced latch-up resistance of majority carrier guards compared to conventional electrode placement. With increasing temperature holding voltage and current decrease for both types. The test devices have also been simulated using 2D FEM device simulation. For majority carrier guard structures it is essential to use Fermi-Dirac-statistics instead of Boltzmann-statistics and a mobility model which accounts for carrier-carrier scattering in order to get accurate simulation results. In a further step the simulations were used to predict the necessary guard width for holding voltages higher than 5V to gain absolutely latch-up free operation at 250 degree(s)C. The results can be exploited for the design of temperature resistant, latch- up free CMOS circuits. The work is relevant for an ongoing effort to make use of junction isolated CMOS technology for temperature resistant electronics up to 250 degree(s)C.