In this paper we present a contribution to create a VHDL-AMS
radio-frequency component library. Currently, integrated circuit
technology tends to integrate in a sole chip not only mixed signal but
also mixed technology systems, going to a more general definition of
the so called Systems On Chip. A library of RF models would be useful
to model, in a same framework, circuits and systems of different
physical domains, including RF, which will certainly optimise design
process of such systems.
Generally, VHDL-AMS, the analogue and mixed signal extension to IEEE
standard VHDL does not include specific formulation for RF devices or
systems modeling, as it does not support distributed parameters for
simulation or description purposes. However, RF devices can be
modeled by means of more general VHDL-AMS resources, like sentences
including algebraic and trigonometric relations.
In this paper, a tool based on free software to perform low level optimization on analog designs is presented. Nowadays, the use of design automation tools for microelectronic circuits design is extending from digital to analog circuits, due in part to the fact that although the analog part of a mixed signal ASIC takes only the 10% of the silicon area, it represents almost 90% of the whole design time. For analog circuits, design process can be divided in two major tasks: topology selection and device sizing. The tool here presented consists on a simulation based optmizh is used to perform automatic low level analog circuit sizing. The tool is composed of three modules: a layout generator, which includes a parasitic extractor, an alaog circuit simulator and a circuit optimizer. The two first modules are respectively Magic and Spice from Berkeley, while the third one, the optimizer, has been developed to evaluate dc, ac, and transient sensitivity simulations performed by Spice and make corrections on the layout sizing. Optimization process starts with a certain topology and standard sized devices, which is then extracted by Magic and simulated by Spice. Performance is evaluated and a sizing correction is proposed. These simulation and corrections are done on an iterative loop until circuit performance reaches design parameters. The tool is demonstrated with an example of a simple analog subcircuit optimization, where parameters like silicon area or power dissipation are optimized, while the circuit keeps on design parameters.
This paper describes implementation of neural network processing layers using basic current-mode operating modules. The research work has been focused on the implementation of neural networks based on the Adaptive Resonance Theory, developed by S. Grossberg and G.A. Carpenter. The ART-based neural network whose operating modules have been choosen for development is the one called MART, proposed by
F. Delgado, because of its complex architecture, auto--adaptive self-learning process, able to discard unmeaningful cathegories. Our presentation starts introducing the behaviour of MART with an analysis of its structure. The development described by this research work is focused on the monochannel block included in the main signal
processing part of the MART neural network. The description of the computing algorithm of the layers inside a monochannel block are also provided in order to show what operational current-mode modules are
needed (multiplier, divider, square-rooter, adder, substractor, absolute value, maximum and minimum evaluator...). Descriptions at schematic and layout levels of all the processing layers are given. All of them have been designed using AMS 0.35 micron technology with a supply voltage of 3.3 volts. The modules are designed to deal with input currents in the range of 20 to 50 microamps, showing a lineal behaviour and an output error of less than 10%, which is good enough for neural signal processing systems. The maximum frecuency of operation is around 200 kHz. Simulation results are included to show that the operation performed by the hardware designed matches the behaviour described by the MART neural network. For testing purposes we show the design of a monochannel block hardware implementation restricted to five inputs and three cathegories.