Smart pixel imaging with computational-imaging arrays (SPICA) transfers image plane coding typically realized in the optical architecture to the digital domain of the focal plane array, thereby minimizing signal-to-noise losses associated with static filters or apertures and inherent diffraction concerns. MIT Lincoln Laboratory has been developing digitalpixel focal plane array (DFPA) devices for many years. In this work, we leverage legacy designs modified with new features to realize a computational imaging array (CIA) with advanced pixel-processing capabilities. We briefly review the use of DFPAs for on-chip background removal and image plane filtering. We focus on two digital readout integrated circuits (DROICS) as CIAs for two-dimensional (2D) transient target tracking and three-dimensional (3D) transient target estimation using per-pixel coded-apertures or flutter shutters. This paper describes two DROICs – a SWIR pixelprocessing imager (SWIR-PPI) and a Visible CIA (VISCIA). SWIR-PPI is a DROIC with a 1 kHz global frame rate with a maximum per-pixel shuttering rate of 100 MHz, such that each pixel can be modulated by a time-varying, pseudorandom, and duo-binary signal (+1,-1,0). Combining per-pixel time-domain coding and processing enables 3D (x,y,t) target estimation with limited loss of spatial resolution. We evaluate structured and pseudo-random encoding strategies and employ linear inversion and non-linear inversion using total-variation minimization to estimate a 3D data cube from a single 2D temporally-encoded measurement. The VISCIA DROIC, while low-resolution, has a 6 kHz global frame rate and simultaneously encodes eight periodic or aperiodic transient target signatures at a maximum rate of 50 MHz using eight 8-bit counters. By transferring pixel-based image plane coding to the DROIC and utilizing sophisticated processing, our CIAs enable on-chip temporal super-resolution.
The advanced imagers team at JHU APL and ECE has been advocating and developing a new class of sensor systems
that address key system level performance bottlenecks but are sufficiently flexible to allow optimization of associated
cost and size, weight, and power (SWaP) for different applications and missions. A primary component of this approach
is the innovative system-on-chip architecture: Flexible Readout and Integration Sensors (FRIS). This paper reports on
the development and testing of a prototype based on the FRIS concept. It will include the architecture, a summary of test
results to date relevant to the hostile fire detection challenge. For this application, this prototype demonstrates the
potential for this concept to yield the smallest SWaP and lowest cost imaging solution with a low false alarm rate. In
addition, a specific solution based on the visible band is proposed. Similar performance and SWaP gains are expected for
other wavebands such as SWIR, MWIR, and LWIR and/or other applications like persistent surveillance for critical
infrastructure and border control in addition to unattended sensors.
We present a bio-inspired system-on-chip focal plane readout architecture which at the system level, relies on an
event based sampling scheme where only pixels within a programmable range of photon flux rates are output.
At the pixel level, a one bit oversampled analog-to-digital converter together with a decimator allows for the
quantization of signals up to 26 bits. Furthermore, digital non-uniformity correction of both gain and offset
errors is applied at the pixel level prior to readout. We report test results for a prototype array fabricated in a
standard 90nm CMOS process. Tests performed at room and cryogenic temperatures demonstrate the capability
to operate at a temporal noise ratio as low as 1.5, an electron well capacity over 100Ge-, and an ADC LSB down