A growing number of commercial products such as displays, solar panels, light emitting diodes (LEDs and OLEDs),
automotive and architectural glass are driving demand for glass with high performance surfaces that offer anti-reflective,
self-cleaning, and other advanced functions. State-of-the-art coatings do not meet the desired performance characteristics
or cannot be applied over large areas in a cost-effective manner. “Rolling Mask Lithography” (RML™) enables highresolution
lithographic nano-patterning over large-areas at low-cost and high-throughput. RML is a photolithographic
process performed using ultraviolet (UV) illumination transmitted through a soft cylindrical mask as it rolls across a
substrate. Subsequent transfer of photoresist patterns into the substrate is achieved using an etching process, which
creates a nanostructured surface. The current generation exposure tool is capable of patterning one-meter long substrates
with a width of 300 mm. High-throughput and low-cost are achieved using continuous exposure of the resist by the
Here, we report on significant improvements in the application of RML™ to fabricate anti-reflective surfaces. Briefly,
an optical surface can be made antireflective by “texturing” it with a nano-scale pattern to reduce the discontinuity in the
index of refraction between the air and the bulk optical material. An array of cones, similar to the structure of a moth’s
eye, performs this way. Substrates are patterned using RML™ and etched to produce an array of cones with an aspect
ratio of 3:1, which decreases the reflectivity below 0.1%.
Step and Flash Imprint Lithography redefines nanoimprinting. This novel technique involves the field-by-field
deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask
is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this
filling step, the resist is crosslinked under UV radiation, and then the mask is removed leaving a patterned solid on the
substrate. Compatibility with existing CMOS processes requires a mask infrastructure in which resolution, inspection
and repair are all addressed. The purpose of this paper is to understand the limitations of inspection at half pitches of 32
nm and below.
A 32 nm programmed defect mask was fabricated. Patterns included in the mask consisted of an SRAM Metal 1
cell, dense lines, and dense arrays of pillars. Programmed defect sizes started at 4 nm and increased to 48 nm in
increments of 4 nm. Defects in both the mask and imprinted wafers were characterized scanning electron microscopy
and the measured defect areas were calculated. These defects were then inspected using a KLA-T eS35 electron beam
wafer inspection system. Defect sizes as small as 12 nm were detected, and detection limits were found to be a function
of defect type.
Imprint lithography has been included on the ITRS Lithography Roadmap at the 32, 22 and 16 nm nodes. Step and
Flash Imprint Lithography (S-FIL ®) is a unique method that has been designed from the beginning to enable precise
overlay for creating multilevel devices. A photocurable low viscosity monomer is dispensed dropwise to meet the
pattern density requirements of the device, thus enabling imprint patterning with a uniform residual layer across a field
and across entire wafers. Further, S-FIL provides sub-100 nm feature resolution without the significant expense of
multi-element, high quality projection optics or advanced illumination sources. However, since the technology is 1X, it
is critical to address the infrastructure associated with the fabrication of templates.
For sub-32 nm device manufacturing, one of the major technical challenges remains the fabrication of full-field 1x
templates with commercially viable write times. Recent progress in the writing of sub-40 nm patterns using commercial
variable shape e-beam tools and non-chemically amplified resists has demonstrated a very promising route to realizing
these objectives, and in doing so, has considerably strengthened imprint lithography as a competitive manufacturing
technology for the sub 32nm node. Here we report the first imprinting results from sub-40 nm full-field patterns, using
Samsung's current flash memory production device design. The fabrication of the template is discussed and the
resulting critical dimension control and uniformity are discussed, along with image placement results. The imprinting
results are described in terms of CD uniformity, etch results, and overlay.
Imprint lithography has been shown to be an effective method for the replication of nanometer-scale
structures from an imprint mask (template) or mold. Step and Flash Imprint Lithography (S-FIL®) is unique in its
ability to address both resolution and alignment. Recently overlay across a 200 mm wafer of less than 20nm, 3σ has
been demonstrated. Current S-FIL resolution and alignment performance motivates the consideration of nano-imprint
lithography as a Next Generation Lithography (NGL) solution for IC production. During the S-FIL process, a
transferable image, an imprint, is produced by mechanically molding a liquid UV-curable resist on a wafer.
Acceptance of imprint lithography for CMOS manufacturing will require demonstration that it can attain defect levels
commensurate with the requirements of cost-effective device production. This report summarizes the result of defect
inspections of wafers patterned using S-FIL. Wafer inspections were performed with KLA Tencor- 2132 (KT-2132)
and KLA Tencor eS23 (KT-eS32) automated patterned wafer inspection tools. Imprint specific defectivity was shown
to be ≤3 cm-2 with some wafers having defectivity of less than 1 cm-2 and many fields having 0 imprint specific
defects, as measured with the KT-2132. KT eS32 inspection of 32 nm half pitch features indicated that the random
defectivity resulting from the imprint process was low.
Imprint lithography has been shown to be an effective method for the replication of nanometer-scale
structures from a template mold. Step and Flash Imprint Lithography (S-FIL®) is unique in its ability to address both
resolution and alignment. Recently overlay across a 200 mm wafer of less than 20nm, 3σ has been demonstrated.
Current S-FIL resolution and alignment performance motivates the consideration of nano-imprint lithography as Next
Generation Lithography (NGL) solution for IC production. During the S-FIL process, a transferable image, an imprint,
is produced by mechanically molding a liquid UV-curable resist on a wafer. The novelty of this process immediately
raises questions about the overall defectivity level of S-FIL. Acceptance of imprint lithography for CMOS
manufacturing will require demonstration that it can attain defect levels commensurate with the requirements of cost-effective
device production. This report specifically focuses on this challenge and presents the current status of defect
reduction in S-FIL technology and will summarize the result of defect inspections of wafers patterned using S-FIL.
Wafer inspections were performed with a KLA Tencor- 2132 (KT-2132) automated patterned wafer inspection tool.
Recent results show wafer defectivity to be less 5 cm-2. Mask fabrication and inspection techniques used to obtain low
defect template will be described. The templates used to imprint wafers for this study were designed specifically to
facilitate automated defect inspection and were made by employing CMOS industry standard materials and exposure
tools. A KT-576 tool was used for template defect inspection.
Researchers have demonstrated that imprint lithography techniques have remarkable replication resolution and can pattern sub-5nm structures. However, a fully capable lithography approach needs to address several challenges in order to be useful in manufacturing. For successful manufacturing insertion of Step and Flash Imprint Lithography (S-FILTM) into a broad set of applications such as photonics, magnetic storage, and integrated circuits (ICs), the following practical process related challenges need to be addressed: (i) Printing sub-50nm structures with non-uniform pattern densities: (ii) Precise alignment and overlay with the ability to mix-and-match with photolithography; (iii) Availability of 1X templates; (iv) Achieving appropriate throughput for acceptable cost of ownership; and (v) Minimizing template and imprint process-induced defects to allow acceptable process yields. The last challenge - the ability to achieve low defect densities - is desirable for all applications. However, it is one of the biggest challenges for S-FIL to be accepted in IC fabrication. This article specifically focuses on this last challenge and presents the current status of defect reduction in S-FIL technology.
The article starts out by providing a brief background of S-FIL technology, and by including a discussion of the overall status of S-FIL technology in Section 1. Next, an overview of the experiments performed including the defect inspection approaches used is provided in Section 2. Section 3 introduces the classes of defects that are relevant to the S-FIL process. It also provides recent defect data for each of these classes. Section 4 presents defect data gathered over the last three years and provides defect reduction trends over this period. Section 5 discusses the topic of template lifetime. Finally Section 6 provides some concluding remarks. The defect data presented here is based on a large number of short-loop experiments based on optical inspection of templates and wafers; these data are complemented by a modest number of high resolution e-beam inspections to provide insight into S-FIL specific defects at leading edge line widths.
Reticle costs are increasing as users tighten specifications to accommodate the shrinking process windows in advanced semiconductor lithography. Tighter specs often drive the use of e-beam based mask processes, which produce better mask pattern acuity than laser-based tools but suffer lower throughput (and thus higher costs). In some cases, such as contacts, the pattern acuity of an e-beam tool does not seem to be required -- but the tight effective CD uniformity typically produced by an e-beam mask writer is still necessary to prevent wafer level defect problems. This presents problems for the maskshop (e.g., low yield and long cycle time) as well as for the fab (more expensive new product introduction, uncertainty in mask delivery). This paper describes the results of qualifying a low cost, high quality mask making process for 90nm wafer production. The process uses a DUV laser-based mask writer to achieve low cost. Wafer photolithography process results using two masks fabricated with different mask making processes are presented, along with comparative electrical performance.
It is well known that shrinking k1 factors are making via and contact layers more difficult to print with acceptable latitude and low defectivity. A typical method for improving the common process window is to use embedded attenuated phase shifting masks (EAPSM). However, even with the improved resolution offered by this technology, small deviations in reticle contact size are producing increasingly severe patterning problems - at the extreme, missing contacts. In this study, we conducted an investigation of a production reticle causing repeating wafer defects that passed the reticle manufacturer’s outgoing inspection. We have examined this reticle using a new inspection algorithm that measures reticle contact energy. This technique successfully detected slightly undersized contacts directly corresponding to the coordinates of the repeating wafer defects.
However, the reticle contact energy inspection also detected numerous undersized contacts that were not detected by wafer SEM inspection. We have produced and printed to wafer a test reticle with programmed over and under sized contacts in order to create a new reticle specification to detect defective contacts before they are shipped to the wafer fab.