In this paper we review the physics and performance of silicon detectors passivated with wafer-scale molecular beam epitaxy (MBE) and atomic layer deposition (ALD). MBE growth of a two-dimensional (2D) doping superlattice on backside-illuminated (BSI) detectors provides nearly perfect protection from interface traps, even at trap densities in excess of 10<sup>14</sup> cm<sup>-2</sup>. Superlattice-doped, BSI CMOS imaging detectors show no measurable degradation of quantum efficiency or dark current from long-term exposure to pulsed DUV lasers. Wafer-scale superlattice-doping has been used to passivate CMOS and CCD imaging arrays, fully-depleted CCDs and photodiodes, and large-area avalanche photodiodes. Superlattice-doped CCDs with ALD-grown antireflection coatings achieved world record quantum efficiency at deep and far ultraviolet wavelengths (100-300nm). Recently we have demonstrated solar-blind, superlattice doped avalanche photodiodes using integrated metal-dielectric coatings to achieve selective detection of ultraviolet light in the 200-250 nm spectral range with high out-of-band rejection.
Imaging systems employed in demanding industrial and military applications such as computer vision and automatic target recognition typically require real-time high- performance computing resources. While these system have traditionally relied on proprietary architectures and custom components, recent advances in high-performance general- purpose microprocessor technology have produced an abundance of low cost components suitable for use in high-performance computing systems.
Imaging systems employed in demanding military and industrial applications, such as automatic target recognition and computer vision, typically require real-time high-performance computing resources. While high- performances computing systems have traditionally relied on proprietary architectures and custom components, recent advances in high performance general-purpose microprocessor technology have produced an abundance of low cost components suitable for use in high-performance computing systems. A common pitfall in the design of high performance imaging system, particularly systems employing scalable multiprocessor architectures, is the failure to balance computational and memory bandwidth. The performance of standard cluster designs, for example, in which several processors share a common memory bus, is typically constrained by memory bandwidth. The symptom characteristic of this problem is failure to the performance of the system to scale as more processors are added. The problem becomes exacerbated if I/O and memory functions share the same bus. The recent introduction of microprocessors with large internal caches and high performance external memory interfaces makes it practical to design high performance imaging system with balanced computational and memory bandwidth. Real word examples of such designs will be presented, along with a discussion of adapting algorithm design to best utilize available memory bandwidth.