The extension of on-board data processing capabilities is an attractive option to reduce telemetry for scientific instruments on deep space missions. The challenges that this presents, however, require a comprehensive software system, which operates on the limited resources a data processing unit in space allows. We implemented such a system for the Polarimetric and Helioseismic Imager (PHI) on-board the Solar Orbiter (SO) spacecraft. It ensures autonomous operation to handle long command-response times, easy changing of the processes after new lessons have been learned and meticulous book-keeping of all operations to ensure scientific accuracy. This contribution presents the requirements and main aspects of the software implementation, followed by an example of a task implemented in the software frame, and results from running it on SO/PHI. The presented example shows that the different parts of the software framework work well together, and that the system processes data as we expect. The flexibility of the framework makes it possible to use it as a baseline for future applications with similar needs and limitations as SO/PHI.
In this paper we present a novel FPGA implementation of the Consultative Committee for Space Data Systems Image Data Compression (CCSDS-IDC 122.0-B-1) for performing image compression aboard the Polarimetric Helioseismic Imager instrument of the ESA’s Solar Orbiter mission. This is a System-On-Chip solution based on a light multicore architecture combined with an efficient ad-hoc Bit Plane Encoder core. This hardware architecture performs an acceleration of ~30 times with respect to a software implementation running into space-qualified processors, like LEON3. The system stands out over other FPGA implementations because of the low resource usage, which does not use any external memory, and of its configurability.
In this contribution we present a multi-core system-on-chip, embedded on FPGA, for real-time data processing, to be used in the Daniel K. Inouye Solar Telescope (DKIST). Our system will provide “quick-look” magnetic field vector and line-of-sight velocity maps to help solar physicists to react to specific solar events or features during observations or to address specific phenomena while analyzing the data off line. The stand-alone device will be installed at the National Solar Observatory (NSO) Data Center. It will be integrated in the processing data pipeline through a software interface, and is competitive in computing speed to complex computer clusters.
In this work we propose a multiprocessor architecture to reach high performance in floating point operations by using radiation tolerant FPGA devices, and under narrow time and power constraints. This architecture is used in the PHI instrument that carries out the scientific analysis aboard the ESA’s Solar Orbiter mission. The proposed architecture, in a SIMD flavor, is aimed to be an accelerator within the Data Processing Unit (it is composed by a main Leon processor and two FPGAs) for carrying out the RTE inversion on board the spacecraft using a relatively slow FPGA device – Xilinx XQR4VSX55–. The proposed architecture squeezes the FPGA resources in order to reach the computational requirements and improves the ground-based system performance based on commercial CPUs regarding time and power consumption. In this work we demonstrate the feasibility of using this FPGA devices embedded in the SO/PHI instrument. With that goal in mind, we perform tests to evaluate the scientific results and to measure the processing time and power consumption for carrying out the RTE inversion.