The Sidewall Spacer Double Patterning (SSDP) technique, also referred to as Self-Aligned Double Patterning (SADP),
has been adopted as the primary double patterning solution for 32nm technology nodes and below for flash memory
manufacturing. Many are now looking to migrate the technique to DRAM and random Logic layers. However, DRAM
and especially Logic have far more complex layout requirements than NAND-FLASH, requiring a more sophisticated
use of the SSDP technique. To handle the additional complexities an automated electronic design tool was used to
calculate optimal layout splits of a design target into 2 or 3 masks. The model was programmed with immersion
lithography and dry-193nm lithography MRC input rules and on wafer performance was tested. We discuss the
patterning needs from the trim-mask and the pad-mask and associated lithography process window requirements and
alignment accuracies necessary to pursue 32nm and 22nm half-pitch designs.
To fulfill Moore's law the R&D stage of 3x nm HP nodes will have to be reached in 2008. Conventional DUV
immersion technology is resolution limited to half pitch values exceeding 40 nm. Double Patterning Technology (DPT)
is a major candidate to reach the 3x nm node in time. Geometrical pattern split, doubling the pitch, is one of the major
steps of DPT. We present a feasibility study of the Rule Based (RB) DPT approach to pattern splitting based on a
representative and reviewed selection of clips and full-mask designs.
DPL (Double Patterning Lithography) has been identified as one of major candidates for 45nm and 32nm HP since
ITRS2006update and several reports of the performance or challenges of DPL have been published. DPL requires
at least two photomasks with tighter specification of image placement and the difference of mean to target
according to ITRS2006update. On the other hand, approximately half of whole features of single layer are written
on each photomask and the densest features are split into other photomask in consequence of pitch relaxation for
DPL. Then the photomask writing data of two sets for DPL and single data for single exposure are evaluated for
photomask fabrication load. The design will be automatically decomposed with EDA tool and OPC will be tuned
as DPL or single exposure. Not only number of fractured features but also feasibility study of automatic
decomposition will be presented and discussed. The consequences of relaxed pitch on process, inspection, repair,
yield, MEEF and cycle time will be discussed with results as available.
A methodology to predict the impact of mask overlay and litho-induced process variations on Statistical
Timing for Double Patterning is presented. As we migrate to the 32nm node and Double Patterning
techniques, Mask Makers, Ebeam providers and Scanner providers are given very aggressive requirements
for maintaining overlay accuracy. This method takes into account Mask CD Uniformity and Mask Image
placement error budgets presented in the 2006 ITRS. It is assumed the ITRS requirements are met. This
methodology combines the infrastructure used in Single Exposure Litho-Aware Layout Implementation
tools with Double Patterning decomposition results to determine a meaningful layout-specific analysis for
pre-tape-out timing sign-off. Traditional timing analysis uses a set of look-up tables for simulating device
distortions. These tables have been proven to require excessive guardbanding in Single Exposure masks.
Adding the additional dimension of overlay distortion to these tables will have the effects of hiding
parametric failures, or requiring excessive guardbanding to ensure timing predictability. Results will be
shown that describe the timing effects with and without taking into account these distortions, as well as
design samples that contribute to these distortions.
In conventional IC processes, the smallest size of any features that can be created on a wafer is severely limited by the pitch of the processing system. Double patterning technology is a key enabler of printing mask features on wafers as a hybrid extension to optical approaches with new litho-aware design methods and tools, optical equipment, and process flows. The approach does not require restrictions on the design of the chip. This paper will discuss the method and full-chip decomposition tool used to determine locations to split the layout. It will demonstrate examples of over-constrained layouts and how these configurations are mitigated. It will also show the reticle enhancement techniques used to process the split layouts and the Lithographic Checking. A new type of "hotspot" is identified through simulation and tools to identify, repair and verify are shown. Lithography results are shown with effective k<sub>1</sub><0.2 for logic and flash memory patterns.
In conventional IC processes, the smallest size of any features that can be created on a wafer is severely limited by the
pitch of the processing system. This approach is a key enabler of printing mask features on wafers without requiring
new manufacturing equipment and with minor changes to existing manufacturing processes. The approach also does not
require restrictions on the design of the chip. This paper will discuss the method and full-chip decomposition tool used to
determine locations to split the layout. It will demonstrate examples of over-constrained layouts and how these
configurations are mitigated. It will also show the reticle enhancement techniques used to process the split layouts and
the Lithographic Checking used to verify the lithographic results.
Subwavelength lithography at low contrast, or low-k1 factor, leads to new requirements for design, design analysis, and design verification techniques. These techniques must account for inherent physical circuit feature distortions resulting from layout pattern-dependent design-to-silicon patterning processes in this era. These
distortions are unavoidable, even in the presence of sophisticated Resolution Enhancement Technologies (RET), and are a 'fact-of-life’ for the designer implementing nanometer-scale designs for the foreseeable low-k1 future. The consequence is that fabricated silicon feature shapes and dimensions are in general printed with far less
fidelity in comparison to the designer’s desired layout than in past generations and that the designer must consider design within significantly different margins of geometry tolerance. Traditional (Mead-Conway originated) WYSIWYG (what you see is what you get) design methodologies, assume that the designer’s physical circuit element shapes are accurate in comparison to the corresponding shapes on the real fabricated IC, and uses design rules to verify satisfactory fabrication compliance, as the input for both
interconnect parasitic loading calculations and to transistor models used for performance simulation. However, these assumptions are increasingly poor ones as k1 decreases to unprecidented levels -- with concomitant increase in patterned feature distortion and fabrication yield failure modes. This paper explores a new paradigm for nanometer-scale design, one in which more advanced models of critical low-k1 lithographic printing effects are incorporated into the design flow to improve upon yield and performance verification accuracy. We start with an analysis of a complex 32-bit adder block circuit design to determine systematic changes in gate length, width and shape variations for each MOSFET in the circuit due to optical
proximity effects. The physical gate dimensions for all, as predicted by the simulations, are then incorporated into the circuit simulation models and netlist (schematic) and are used to calculate the changes in critical parametric yield factors such as timing and power consumption in the circuit behavior. These functional consequences create a manufacturability tolerance requirement that relates to function and parametric yield, not just physical manufacturability. We then explore the improvements in functional attributes and manufacturability that arise from systematic correction of these distortions by RET including; simulation-driven model-based OPC,
alternating-aperture PSM (altPSM), and altPSM+OPC. This analysis is just one dimension of a systmatic methodology that incorporates lithographic effects into a design for manufacturing (DFM) scheme. The benefits promise dramatically improved silicon-signoff verification, predictive performance and yield analysis, and more
cost-effective application of RET.
As we delve deeper into subwavelength design and manufacturing challenges and solutions, technologies such as Optical Proximity Correction (OPC) and Phase Shifting Masks (PSM) have become essential to reliabily produce advanced integrated circuits. Alternating PSM (altPSM) has demonstrated many recent successses as an effective means to this end. This paper lays the groundwork for defining the IC design components needed to meet altPSM-compliance requirements. The paper addresses the open question regarding whether we can take into account all the manufacturing requirements and come up with highly abstract manufacturing rules that can be applied to all IC design domains. The paper further proposes a solution with specific rules and algorithms needed to apply altPSM to transistor gate regions, and targeted to various domains of IC design such as verification or place and route. Examples include constraints for routers and placement tools, as well as sign-off rules that can be used by designers as well as by production engineres to fine-tune the process and yield for a given design structure. The usability of such a solution is then analyzed to take the practical aspects of IC design into consideration.