The Associative Mesh, a reconfigurable, asynchronous and massively parallel SIMD architecture, is a hardware transposition of the Associative Nets model, where each entity, to achieve maximal efficiency, is supposed to stand for one pixel of an image. Global operations in the circuit are performed using an asynchronous electronic. This implementation allows for a very fast computation time - about a microsecond - and with a crossing time of each processor of about a nanosecond. Asynchronism also allows the design to save area, power and reach a higher clock frequency. Most of the image analysis algorithns for 2D or 3D set of datas can be implemented using the Associative Mesh. Our objective is to implement a full-size Associative Mesh with a SoC aim. To achieve this, we have studied the contribution of processors' virtualisation. We show that, provided a reorganisation of the synchronous part of the circuit, it offers a significant area gain which increases with the degree of virtualisation (reaching 20% for a degree equal to 16). We also discuss how virtualisation preserves the architecture's performances, and is useful to adapt the circuit to 3D treatments. Algorithm evaluations show that this architecture is compatible with real-time 2D and 3D image processing.
In this article, we present a popular loseless compression/decompression algorithm, GZIP, and the study to implement it on a FPGA based architecture. The algorithm is loseless, and applied to 'bi-level' images of large size. It insures a minimum compression rate for the images we are considering. The proposed architecture for the compressor is based ona hash table and the decompressor is based on a parallel decoder of the Huffman codes.