Process-window (PW) evaluation is critical to assess the lithography process quality and limitations. Usual CD-based PW gives only a partial answer. Simulations such as Tachyon LMC (Lithography Manufacturability Check) can efficiently overcome this limitation by analyzing the entire predicted resist contours. But so far experimental measurements did not allow such flexibility. This paper shows an innovative experimental flow, which allows the user to directly validate LMC results across PW for a select group of reference patterns, thereby overcoming the limitations found in the traditional CD-based PW analysis. To evaluate the process window on wafer more accurately, we take advantage of design based metrology and extract experimental contours from the CD-SEM measurements. Then we implement an area metric to quantify the area coverage of the experimental contours with respect to the intended ones, using a defined “sectorization” for the logic structures. This ‘sectorization’ aims to differentiate specific areas on the logic structures being analyzed, such as corners, line-ends, short and long lines. This way, a complete evaluation of the information contained in each CD-SEM picture is performed, without having to discard any information. This solution doesn’t look at the area coverage of an entire feature, but uses a ‘sectorization’ to differentiate specific feature areas such as corners, line-ends, short and long lines, and thus look at those area coverages. An assessment of resist model/OPC quality/process quality at sub nm-level accuracy is rendered possible.
As ArF immersion lithography continues to be extended by adopting multi-patterning techniques, imaging requirements continue to become more stringent [1-3]. For multiple patterning based logic devices, the optimal printability is not only driven by the optimization of the optical proximity correction (OPC), but also by complex process factors, such as resist, exposure tool, and mask-related error performance levels. In addition the light source plays a crucial role; it has been widely demonstrated [4-8] how changes in the E95 bandwidth can significantly lead to changes in on wafer patterning due image contrast changes. Cymer has developed novel computational and experimental approaches to enable process characterization studies [9-11]. Using these techniques, simulations were used to assess how E95 bandwidth changes can erode the CDU budget on ≤ 20 nm logic features. Using the results of these simulations, experimental conditions were defined to study the on wafer impact of light source performance on an imec N10 Logic-type test vehicle via six different Metal 1 Logic features. The imaging metrics used to track patterning response are process window (PW), line width roughness (LWR), and local critical dimension uniformity (LCDU).
Lithography process window (PW) and CD uniformity (CDU) requirements are being challenged with scaling across all device types. Aggressive PW and yield specifications put tight requirements on scanner performance, especially on focus budgets resulting in complicated systems for focus control. In this study, an imec N10 Logic-type test vehicle was used to investigate the E95 bandwidth impact on six different Metal 1 Logic features. The imaging metrics that track the impact of light source E95 bandwidth on performance of hot spots are: process window (PW), line width roughness (LWR), and local critical dimension uniformity (LCDU).
In the first section of this study, the impact of increasing E95 bandwidth was investigated to observe the lithographic process control response of the specified logic features. In the second section, a preliminary assessment of the impact of lower E95 bandwidth was performed. The impact of lower E95 bandwidth on local intensity variability was monitored through the CDU of line end features and the LWR power spectral density (PSD) of line/space patterns. The investigation found that the imec N10 test vehicle (with OPC optimized for standard E95 bandwidth of300fm) features exposed at 200fm showed pattern specific responses, suggesting areas of potential interest for further investigation.
EUV stochastic effects are generally studied [1-7] from the point of view of Line-Edge-Roughness (LER), Line-Width-Roughness (LWR), Local CDU (LCDU), i.e. from the point of view of the CD-Variability of the printed patterns. In this paper we will look at what happens when this variability gets worse and turns into (random) locally failing patterns, such as missing contacts or locally closed trenches. In doing so, these failures contribute to setting the effective printability limit for the experimental conditions and the type of structures that are being considered. We will first discuss the way in which we have tried to quantify the amount of locally failing structures, i.e. the metrics we have adopted to describe them. Next we describe how the amount of locally failing structures depends on some pattern-related and experimental condition-related parameters. From this we concluded that – as in the case of local variability – the amount of local failure depends on the exposure dose used (the well-known photon shot noise effects) as well as on mechanisms that originate in the resist or the process. Although we have not been able to identify what this resist- or materials component is exactly, we do have some indications that point to the development step, but we will also discuss other potential contributors.
We developed a new measurement method enabling to quantitatively and accurately evaluate 2D pattern shapes, which becomes critical in patterning control of Metal layer patterns transferred by Litho-Etch-Litho-Etch (LELE) process. In LELE, a split patterning of a Metal-A (MA) layer and a Metal-B (MB) layer makes patterning control more challenging. Hence, it is essential to evaluate the shape of transferred patterns after final etching in order to verify that the patterning control of MA and MB layer patterns is performed within an allowable budget. For this, our Pattern Shape Quantification (PSQ) method , which enables to measure dimensional difference of the transferred pattern shape from their target-design, is an effective metrology. Patterns transferred through a LELE process contain the effects of two types of shape modifications. The first is the fidelity of the individual pattern shapes (e.g. pattern-end pull-back or push-out) whose determinative factors are adopted design (e.g. OPC and SRAF), process condition (of e.g. lithography and etching), etc. The second is the shift in position between MA and MB patterns induced by Pattern Placement Error (PPE) of MB with respect to MA. That means that the edge-placement errors (EPE) in the final pattern are not only due to the fidelity of the transferred pattern shape, but are also impacted by the PPE. Also, a space between MA and MB patterns will be affected by the PPE as well. A failure to maintain a required minimum space between patterns could lead to a leak-current between patterns (and hence directly affect device performance), so it is important that the PPE can be measured accurately. Therefore, we developed a method to measure local PPE in actual device patterns, from CD-SEM images, that also outputs a pattern-contour in which this PPE has been removed. Utilizing such a pattern-contour into the PSQ method enables to quantitatively determine the fidelity of transferred pattern shape solely induced by the 1st shape modification, while providing PPE data from the device patterns themselves. We believe that a high-quality patterning control (by e.g. optimization of process condition) of MA and MB can be performed only by using such a measurement result. This paper demonstrates and discusses the capability and effectiveness of our newly developed method.
The extension of 193nm immersion lithography to the 14nm node and beyond directly encounters a
significant reduction in image quality. One of the consequences is that the resist profile varies noticeably,
impacting the already limited process window. Resist top-loss, top-rounding, T-top and footing all play
significant roles in the subsequent etch process. Therefore, a reliable rigorous model with the capability to
correctly predict resist 3D (R3D) profiles is acquiring higher importance. In this paper, we will present a
calibrated rigorous model of a negative-tone develop resist. Resist profiles can be well simulated through
focus and dose, and cases that match well to the experimental wafer data are validated. Such a model can
not only provide early investigation of insights into process limitation and optimization, but can also
complement existing OPC models to become R3D-aware in process development.
A Metal1-layer (M1) patterning study is conducted on 20nm node (N20) for random-logic applications. We quantified the
printability performance on our test vehicle for N20, corresponding to Poly/M1 pitches of 90/64nm, and with a selected
minimum M1 gap size of 70nm. The Metal1 layer is patterned with 193nm immersion lithography (193i) using Negative
Tone Developer (NTD) resist, and a double-patterning Litho-Etch-Litho-Etch (LELE) process. Our study is based on Logic
test blocks that we OPCed with a combination of calibrated models for litho and for etch. We report the Overlapping
Process Window (OPW), based on a selection of test structures measured after-etch. We find that most of the OPW limiting
structures are EOL (End-of-Line) configurations. Further analysis of these individual OPW limiters will reveal that they
belong to different types, such as Resist 3D (R3D) and Mask 3D (M3D) sensitive structures, limiters related to OPC
(Optical Proximity Corrections) options such as assist placement, or the choice of CD metrics and tolerances for calculation
of the process windows itself. To guide this investigation, we will consider a ‘reference OPC’ case to be compared with
other solutions. In addition, rigorous simulations and OPC verifications will complete the after-etch measurements to help
us to validate our experimental findings.
Logic manufacturers are looking towards a triple patterning solution for their 10nm node Metal1 layer, and possibly for Via0, and local interconnect layers. Given the NP-completeness for the 3-colorability problem, a challenge is how to go beyond a standard cell to efficiently decompose a layout at a block or chip level. Using decomposed or pre-colored standard cells does not always mean decomposable standard cell layouts can be placed next to each other. Posing constraints on how cells can be placed next to each other could cause area loss. A preferred way is to perform the decomposition at a block or chip level.
We have successfully developed a triple patterning decomposition methodology that can effectively decompose an entire layout block or a chip. Formulating a triple patterning decomposition problem into a graph 3-color problem, the system first builds a graph to represent the layout. It then tries to reduce and partition the graph without changing its 3-colorability property. To color the reduced graph, we adopt a hybrid approach with a fast heuristic for coloring and an exact coloring algorithm for backup and conflict verification.
Unlike an odd cycle in double patterning, a triple patterning coloring conflict can’t be represented in a single loop.
Another challenge for triple patterning is then how to report errors that the user can effectively use to fix them. For this purpose, minimum fix guidance – minimum to fix a conflict, and maximal minimum fix guidance – maximal choices are presented.
In this work, 3D mask modeling capabilities of Calibre will be used to assess mask topography impact on EUV imaging.
The EUV mask absorber height and the non-telecentric illumination at mask level, modulate the captured intensity from
the shadowed mask area through the reflective optics on to the wafer, named as the mask shadowing effect. On the other
hand, thinning the mask absorber height results in unwanted background intensity, or called flare. A true compromise
has to be taken into account for the height parameter of a EUV mask absorber. We will discuss the state-of-the-art 3D
mask modeling capabilities, and will present methodologies to tackle the described EUV mask shadowing effect in
Calibre software. The findings will be validated against experiments on ASML's NXE:3100 EUV scanner at imec.
Masks with two different absorber heights will be evaluated on various combinations of features containing line/space
As semiconductor lithography is pushed to smaller dimensions, the process yields tend to suffer due to subwavelength
imaging effects. In response, resolution enhancement technologies have been employed together with
optimization techniques, specifically source mask optimization (SMO), which finely tunes the process by
simultaneously optimizing the source shape and mask features. However, SMO has a limitation in that it fails to
compensate for undesired phase effects. For mask features on the order of the wavelength, the topography of the
mask can induce aberrations which bring asymmetry to the focus-exposure matrix (FEM) and ultimately decrease
the process window. This paper examines the dependency of FEM asymmetry on factors such as the illumination
coherency and lens induced spherical aberration. It is shown that lens induced primary spherical aberration strongly
impacts the symmetry of the FEM. In this work, phase correction is achieved by incorporating the pupil plane in an
optimization. It is shown that primary spherical aberration can correct for effects including the degraded depth of
focus and the tilt in the FEM for a dual trench mask. A pupil function with an optimized coefficient of primary
spherical aberration balances the spherical aberration induced by the mask topography.
We report on the investigation of lateral diffusion of minority carriers in InAsSb based photodetectors with
the nBn design. Diffusion lengths (DL) were extracted from temperature dependent I-V measurements. The
behavior of DL as a function of applied bias, temperature, and composition of the barrier layer was
investigated. The obtained results suggest that lateral diffusion of minority carriers is not the limiting factor
for InAsSb based nBn MWIR detector performance at high temperatures (> 200K). The detector with an As
mole fraction of 10% in the barrier layer has demonstrated values of DL as low as 7 μm (Vb = 0.05V) at 240K.
Our group is investigating nBn detectors based on bulk InAs(1-x)Sb(x) absorber (n) and contacts (n) with an AlAs(1-x)Sb(x)
barrier (B). The wide-band-gap barrier material exhibits a large conduction band offset and small valence band offset
with respect to the narrow-band-gap absorber material. An important matter to explore in this design is the barrier
parameters (material, composition and doping concentration) and how they effect the operation of the device. This paper
investigates AlAs(1-x)Sb(x) barriers with different compositions and doping levels and their effect on detector
characteristics, in particular, dark current density, responsivity and specific detectivity.