Techniques for identifying and mitigating effects of process variation on the electrical performance of integrated circuits
are described. These results are from multi-discipline, collaborative university-industry research and emphasize
anticipating sources of variation up-stream early in the circuit design phase. The lithography physics research includes
design and testing electronic monitors in silicon at 45 nm and
fast-CAD tools to identify systematic variations for entire
chip layouts. The device research includes the use of a spacer (sidewall transfer) gate fabrication process to suppress
random variability components. The Design-for-Manufacturing research includes double pattern decomposition in the
presence of bimodal CD behavior, process-aware reticle inspection, tool-aware dose trade-off between leakage and
speed, the extension of timing analysis methodology to capture across process-window effects and electrical processwindow
A fast-CAD method for evaluating through-focus interaction among features is developed based on dual layout
convolution kernels derived and tested for accuracy in predicting intensity changes. The model is derived by extending
the Taylor series expansion for OPD to include a quadratic term, resulting in not only the usual pattern match factor Z<sub>3</sub>
for defocus, but also match factors for Z<sub>0</sub> and Z<sub>8</sub>. The model is tested through-focus on a logic layout and the predicted
intensity change versus the actual intensity change through-focus is graphed. Results for basic case near coherent
illumination show an R<sup>2</sup> of 0.92. Generalization to use only two patterns instead of three is shown to work well for line
ends, with an R<sup>2</sup> of 0.96.
A tiny footprint electrically probable single layer defocus monitor/test structure has been designed and tested to show
sub-10nm resolution in electrical or electronic defocus monitoring. Electronic testing is a low-cost must have for on-chip
production process monitoring which will become necessary for effective Design for Manufacturing. This programmable
defocus monitor can be designed to pinch open at various levels of defocus by modifying four different layout
parameters, CD, probe size, offset, and the number of rings. An array of these structures can be read as a series of opens
and shorts, or 1s and 0s, to electronically extract defocus. One important feature of this defocus test structure is that it has
an asymmetric response through focus, which translates to a high sensitivity to defocus at low defocus values or close to
nominal conditions. Simulation and experimental results have shown good sensitivity for both on axis, tophat, and offaxis,
quasar, illumination. This paper will present both simulation and experimental results that demonstrate the
programmability and sensitivity of this test structure to defocus.
Pattern matching methods are examined as fast-CAD tools for full-chip across process window examination of postdecomposition
double patterning layouts. The goal is to demonstrate the ability to anticipate lithographic weakness due
to many sources. This includes the decomposition strategy itself, OPC of individual sub-layers, focus-exposure process
window and illumination. This study is an intermediate step to using fast-CAD assessment tools within pattern
decomposition algorithms to guide decisions based on lateral influences instead of rules. The accuracy of the pattern
matcher as a method for hot spot detection is investigated, and a model relating coma match factors and edge movement
is refined to have an R<sup>2</sup> value of 0.95. The validity of the pattern matcher is explored by relating pre-OPC matches to
post-OPC matches, and by showing that the lateral influence functions for Z<sub>0</sub> and Z<sub>3</sub> have high matches at distinct
locations, implying that OPC which corrects for one of Z<sub>0</sub> and <sub>Z3</sub> will not necessarily correct for the other. The pattern
matcher is run on a post decomposition layout and locations are identified with high variability under coma, and their
sensitivity is verified with aerial image simulations. For one such example, a different split is made and the match factor
drops by 55%.
Self-interferometric electrically measurable image focus monitors have been designed and tested in photoresist in a
double exposure implementation. The Pattern-and-Probe monitors for this experiment were placed on a multiple student
phase shift mask, and were validated by means of SEM images in photoresist on wafers shot at 193nm with an NA of
0.85, with 40nm focus steps. A large number of monitor parameters were varied in the experiment, such as the number
of rings, linewidth and center probe size, and recommendations for the optimal combination of parameters for the design
are given. Misalignment is accounted for by placing multiple patterns on the mask, translated a small amount so that at
least one will be centered exactly over the line. The results exhibit sufficient sensitivity to produce an open circuit after
0.3 - 0.6 Rayleigh Units defocus, and thus detect when the process is at the edge of the process window.
Exploratory prototype DfM tools, methodologies and emerging physical process models are described. The examples
include new platforms for collaboration on process/device/circuits, visualization and quantification of manufacturing
effects at the mask layout level, and advances toward fast-CAD models for lithography, CMP, etch and photomasks. The
examples have evolved from research supported over the last several years by DARPA, SRC, Industry and the Sate of
California U.C. Discovery Program. DfM tools must enable complexity management with very fast first-cut accurate
models across process, device and circuit performance with new modes of collaboration. Collaborations can be promoted
by supporting simultaneous views in naturally intuitive parameters for each contributor. An important theme is to shift
the view point of the statistical variation in timing and power upstream from gate level CD distributions to a more
deterministic set of sources of variations in characterized processes. Many of these nonidealities of manufacturing can be
expressed at the mask plane in terms of lateral impact functions to capture effects not included in design rules. Pattern
Matching and Perturbation Formulations are shown to be well suited for quantifying these sources of variation.
A multi-student testchip aimed at characterizing lithography related variations with over 15,000 individually probable
test structures and transistors has been designed and a complementary 65nm process flow and data aggregation strategy
have also been implemented. Test structures have been strategically designed to have high sensitivities to non-idealities
such as defocus, LWR, misalignment and other systematic sources of variation. To enable automated measurement of
massive amounts of test structures, Enhanced Transistor Electrical CD (Critical Dimension) metrology has been used as
it offers high pattern density and almost no geometrical restrictions. Electrical testing at cryogenic temperatures will be
employed to study the impact of Line Width Roughness (LWR) versus Random Dopant Fluctuations (RDF), which will
not play a significant role at cryogenic temperatures, 4K. To facilitate data analysis and comparison of results between
students, a relational database has been designed and implemented. The database will be web accessible for each student
to use and update. It will serve as a collaborative platform for reinforcing conclusions, filtering out confounding data,
and involving outside parties that are interested in process variations at the 65nm node. Experimental data was not
available at the time this paper was written, so this paper will concentrate on the design and simulation results of test
This paper considers modifications of the Pattern-and-Probe monitors to make them suitable for including within the
circuit design as drop in monitors for the lithography process. Nonidealities such as lens aberrations can be monitored
through patterns derived from the Zernike polynomials. However, the non-Manhattan geometries produced by this
theoretical method are not mask friendly, and in fact took many hours to manufacture in their first attempt. This paper
presents modifications to original aberration monitors to allow them to pass DRC checks and thus be more mask-friendly.
Additionally, the original patterns' quantitative interpretation also requires over exposure sequences, special
SEM reading of dots instead of linewidth, and separate calibration of the EM performance of the central reference probe.
The principles expressed in the original aberration monitors can be integrated into more traditional circuit layouts to
create more processing acceptable patterns, with the example shown in this paper retaining 68% of it sensitivity and no
decrease in orthogonality.
A new method for analysis of variation and yield across the whole chip is presented. This method takes into account the
stochastic distribution of the input process parameters such as focus and exposure, and performs simulations of the
design at the extreme points of the process window. Using a robust model to extrapolate the points within the process
window, a full distribution of CDs is produced for each gate, which then is analyzed to provide information about both
the individual gate and the variation across the chip.
An exploratory Process Variation Net Scanning (PVNS) approach to estimate interconnect delay variations is presented.
It is shown that the geometrical response of lithographic nonidealities can be quickly predicted to first order with Pattern
Matching. This concept can be extended to other process nonidealities by developing Maximum Lateral Impact
Functions to capture the effects of variations in conductor sidewall angle and thickness from etch and CMP processes.
The geometrical response for each variation can then be used to model the effective change in resistance and capacitance
and perturb the corresponding values in the extracted netlist. The impact of PVNS is demonstrated using a 90nm digital
design, and the runtime analysis indicates that this approach may potentially be twice as fast as traditional extraction.
This allows for fast electrical analysis of independent process variations on different interconnect layers instead of
traditional best and worst case corner analyses.
Self-interferometric based electrical test patterns are proposed for highly-sensitive systematic projection printing field mapping and production wafer monitoring. The strategy is to adapt the high sensitivity of Pattern-And-Interferometric-Probe monitors for aberrations to electrical testing by means of short loop and within process flow process step sequences. For this application the measurement of the presence or absence of contact sized hole in the resist in a focus-exposure matrix would be replaced by the creation of an electrical open or short in a nominally conducting minimum sized feature. Both double exposure and single exposure test patterns are presented. Detailed image simulations have been used to demonstrate the principles, create layout designs, characterize performance and compare the enhanced sensitivity relative to typical circuit layout features. Sensitivities of 8% of the clear field per 0.01λ RMS have been verified through simulation of the electrical test pattern. Layouts of these patterns have been placed on multiple-student PSM test reticles for future experimental validation.
A pattern matching technique for quickly scanning layouts to find 'worst case' printing problems has been extended to and tested for accuracy on a progressive sequence of advances in optical lithography, including off-axis illumination, attenuated masks, optical-proximity correction and double exposure treatments. These extensions required including phase-variations from off-axis sources with the usual method for production of Maximum Lateral Test Patterns, and utilizing a composite match factor computer from McIntyre et al. to give a vulnerability score. Direct aerial image simulation of the projection printing of the local pattern shows that the basic trends are correctly extracted at high-speed with pattern matching. Pattern matching is found to be a useful tool under these technologies for prescreening layouts to find the most sensitive areas to residual effects, and also for quick comparison of worst case issues among different lithography treatments.