In next generation 3D-NAND devices, accurately determining after-etch overlay for the multi-layer stack is a major challenge. This is especially the case for the multi-tier 3D-NAND structures, where the overlay of the channel holes is an important performance parameter. The most commonly used after-etch metrology suffer both from the high aspect ratio of the channel holes and from the potential presence of large tilts. <p> </p>Using In-Device Metrology (IDM), we show results of non-destructive overlay measurements on 3D-NAND memory holes. Once the overlay signal has been determined, the remaining asymmetry information in the measurement can be used to characterize tilt phenomena densely through the memory array. <p> </p>Using hyper-dense in-device measurements show the overlay effects of intra-die stress. A new lithography scanner model is used to correct specifically for such intra-die overlay fingerprints.