Dr. Jung-Hoon Ser Profile

Dr. Jung-Hoon Ser

Principal Engineer at ASML US

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Author

Area of Expertise:

Semiconductor Lithography , Computational Lithography , Semiconductor Laser

Publications (8)

Proceedings Article | 20 March 2018 Presentation + Paper

Efficient full-chip SRAF placement using machine learning for best accuracy and improved consistency

Shibing Wang, Stanislas Baron, Nishrin Kachwala, Chidam Kallingal, Dezheng Sun, Vincent Shu, Weichun Fong, Zero Li, Ahmad Elsaid, Jin-Wei Gao, Jing Su, Jung-Hoon Ser, Quan Zhang, Been-Der Chen, Rafael Howell, Stephen Hsu, Larry Luo, Yi Zou, Gary Zhang, Yen-Wen Lu, Yu Cao

Proc. SPIE. 10587, Optical Microlithography XXXI

KEYWORDS: Lithography, Image processing, Photomasks, Machine learning, Source mask optimization, Computational lithography, Optical proximity correction, SRAF, Model-based design

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Various computational approaches from rule-based to model-based methods exist to place Sub-Resolution Assist Features (SRAF) in order to increase process window for lithography. Each method has its advantages and drawbacks, and typically requires the user to make a trade-off between time of development, accuracy, consistency and cycle time.

Rule-based methods, used since the 90 nm node, require long development time and struggle to achieve good process window performance for complex patterns. Heuristically driven, their development is often iterative and involves significant engineering time from multiple disciplines (Litho, OPC and DTCO).

Model-based approaches have been widely adopted since the 20 nm node. While the development of model-driven placement methods is relatively straightforward, they often become computationally expensive when high accuracy is required. Furthermore these methods tend to yield less consistent SRAFs due to the nature of the approach: they rely on a model which is sensitive to the pattern placement on the native simulation grid, and can be impacted by such related grid dependency effects. Those undesirable effects tend to become stronger when more iterations or complexity are needed in the algorithm to achieve required accuracy.

ASML Brion has developed a new SRAF placement technique on the Tachyon platform that is assisted by machine learning and significantly improves the accuracy of full chip SRAF placement while keeping consistency and runtime under control. A Deep Convolutional Neural Network (DCNN) is trained using the target wafer layout and corresponding Continuous Transmission Mask (CTM) images. These CTM images have been fully optimized using the Tachyon inverse mask optimization engine. The neural network generated SRAF guidance map is then used to place SRAF on full-chip. This is different from our existing full-chip MB-SRAF approach which utilizes a SRAF guidance map (SGM) of mask sensitivity to improve the contrast of optical image at the target pattern edges.

In this paper, we demonstrate that machine learning assisted SRAF placement can achieve a superior process window compared to the SGM model-based SRAF method, while keeping the full-chip runtime affordable, and maintain consistency of SRAF placement . We describe the current status of this machine learning assisted SRAF technique and demonstrate its application to full chip mask synthesis and discuss how it can extend the computational lithography roadmap.

Proceedings Article | 5 April 2011 Paper

Investigation of EUV tapeout flow issues, requirements, and options for volume manufacturing

Jonathan Cobb, Sunghoon Jang, Junghoon Ser, Insung Kim, Johnny Yeap, Kevin Lucas, Munhoe Do, Young-Chang Kim

Proc. SPIE. 7969, Extreme Ultraviolet (EUV) Lithography II

KEYWORDS: Lithography, Reticles, Optical lithography, Manufacturing, Photomasks, Extreme ultraviolet, Extreme ultraviolet lithography, Optical proximity correction, Model-based design, 193nm lithography

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Although technical issues remain to be resolved, EUV lithography is now a serious contender for critical layer patterning of upcoming 2X node memory and 14nm Logic technologies in manufacturing. If improvements continue in defectivity, throughput and resolution, then EUV lithography appears that it will be the most extendable and the cost-effective manufacturing lithography solution for sub-78nm pitch complex patterns. EUV lithography will be able to provide a significant relaxation in lithographic K1 factor (and a corresponding simplification of process complexity) vs. existing 193nm lithography. The increased K1 factor will result in some complexity reduction for mask synthesis flow elements (including illumination source shape optimization, design pre-processing, RET, OPC and OPC verification). However, EUV does add well known additional complexities and issues to mask synthesis flows such as across-lens shadowing variation, across reticle flare variation, new proximity effects to be modeled, significant increase in pre-OPC and fracture file size, etc. In this paper, we investigate the expected EUV-specific issues and new requirements for a production tapeout mask synthesis flow. The production EUV issues and new requirements are in the categories of additional physical effects to be corrected for; additional automation or flow steps needed; and increase in file size at different parts in the flow. For example, OASIS file sizes after OPC of 250GigaBytes (GB) and files sizes after mask data prep of greater than three TeraBytes (TB) are expected to be common. These huge file sizes will place significant stress on post-processing methods, OPC verification, mask data fracture, file read-in/read-out, data transfer between sites (e.g., to the maskshop), etc. With current methods and procedures, it is clear that the hours/days needed to complete EUV mask synthesis mask data flows would significantly increase if steps are not taken to make efficiency improvements. Therefore, we also analyze different options for reducing or alleviating the EUV specific issues mentioned above and the expected cost/benefit tradeoffs associated with these options. The options include understanding the accuracy vs. run-time benefit of different rule-based and model-based approaches for several correction issues; predicting the implications and improvements expected with different flow automation options; and estimating possible productivity improvements with different flow parallelization choices and upcoming multi-core processors. Optimal combinations of options and accuracy/effort/runtime results can be seen to enable EUV lithography tapeout flows to achieve equal or better total time when compared to current 193nm optical lithography tapeout flow times.

Proceedings Article | 23 March 2011 Paper

Investigating the performance of directional boundary layer model through staged modeling method

Moon-Gyu Jeong, Won-Chan Lee, Seung-Hune Yang, Sung-Hoon Jang, Seong-Bo Shim, Young-Chang Kim, Chun-Suk Suh, Seong-Woon Choi, Young-Hee Kim

Proc. SPIE. 7973, Optical Microlithography XXIV

KEYWORDS: Cadmium, Data modeling, Error analysis, Photomasks, Artificial intelligence, Optical proximity correction, Neodymium, Semiconducting wafers, Statistical modeling, Performance modeling

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Generally speaking, the models used in the optical proximity effect correction (OPC) can be divided into three parts, mask part, optic part, and resist part. For the excellent quality of the OPC model, each part has to be described by the first principles. However, OPC model can't take the all of the principles since it should cover the full chip level calculation during the correction. Moreover, the calculation has to be done iteratively during the correction until the cost function we want to minimize converges. Normally the optic part in OPC model is described with the sum of coherent system (SOCS[1]) method. Thanks to this method we can calculate the aerial image so fast without the significant loss of accuracy. As for the resist part, the first principle is too complex to implement in detail, so it is normally expressed in a simple way, such as the approximation of the first principles, and the linear combinations of factors which is highly correlated with the chemistries in the resist. The quality of this kind of the resist model depends on how well we train the model through fitting to the empirical data. The most popular way of making the mask function is based on the Kirchhoff's thin mask approximation. This method works well when the feature size on the mask is sufficiently large, but as the line width of the semiconductor circuit becomes smaller, this method causes significant error due to the mask topography effect. To consider the mask topography effect accurately, we have to use rigorous methods of calculating the mask function, such as finite difference time domain (FDTD[2]) and rigorous coupled-wave analysis (RCWA[3]). But these methods are too time-consuming to be used as a part of the OPC model. Until now many alternatives have been suggested as the efficient way of considering the mask topography effect. Among them we focused on the boundary layer model (BLM) in this paper. We mainly investigated the way of optimization of the parameters for the BLM since the feasibility of the BLM has been investigated in many papers[4][5][6]. Instead of fitting the parameters to the wafer critical dimensions (CD) directly, we tried to use the aerial image (AI) from the rigorous simulator with the electromagnetic field (EMF) solver. Usually that kind of method is known as the staged modeling method. To see the advantages of this method we conducted several experiments and observed the results comparing the method of fitting to the wafer CD directly. Through the tests we could observe some remarkable results and confirmed that the staged modeling had better performance in many ways.

Proceedings Article | 23 March 2011 Paper

Fine calibration of physical resist models: the importance of Jones pupil, laser bandwidth, mask error and CD metrology for accurate modeling at advanced lithographic nodes

Seongho Moon, Seunghune Yang, Artem Shamsuarov, Eunju Kim, Junghoon Ser, Youngchang Kim, Seongwoon Choi, Changjin Kang, Ulrich Klostermann, Bernd Küchler, John Lewellen, Thomas Schmöller, Sooryong Lee

Proc. SPIE. 7973, Optical Microlithography XXIV

KEYWORDS: Metrology, Cadmium, Data modeling, Calibration, 3D modeling, Scanning electron microscopy, Photomasks, Optical proximity correction, Critical dimension metrology, Laser metrology

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Proceedings Article | 23 March 2011 Paper

Hotspot fixing using ILT

Woojoo Sim, Sunggon Jung, Hyun-Jong Lee, Sungsoo Suh, Jung-Hoon Ser, Seong-Woon Choi, Chang-Jin Kang, Thomas Cecil, Christopher Ashton, David Irby, Xin Zhou, D.H. Son, Guangming Xiao, David Kim

Proc. SPIE. 7973, Optical Microlithography XXIV

KEYWORDS: Lithography, Photovoltaics, Data modeling, Calibration, Photomasks, Optical proximity correction, SRAF, Nanoimprint lithography, Semiconducting wafers, Resolution enhancement technologies

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Proceedings Article | 29 September 2010 Paper

Improving model prediction accuracy for ILT with aggressive SRAFs

Sunggon Jung, Woojoo Sim, Moongyu Jeong, Junghoon Ser, Sungwoo Lee, Seoung-woon Choi, Xin Zhou, Lan Luan, Thomas Cecil, Donghwan Son, Robert Gleason, David Kim

Proc. SPIE. 7823, Photomask Technology 2010

KEYWORDS: Lithography, Calibration, Diffusion, Scanning electron microscopy, Photomasks, Cadmium sulfide, Optical proximity correction, SRAF, Critical dimension metrology, Performance modeling

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Proceedings Article | 25 September 2010 Paper

New method to determine process window considering pattern failure

Seung-Hune Yang, Seongho Moon, Junghoon Ser, Young-Chang Kim, Sung-Woon Choi, Chang-Jin Kang

Proc. SPIE. 7823, Photomask Technology 2010

KEYWORDS: Lithography, Image processing, Remote sensing, Image analysis, Optical inspection, Bridges, Critical dimension metrology, Line edge roughness, Semiconducting wafers, Failure analysis

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Proceedings Article | 22 March 2010 Paper

Comparison of OPC models with and without 3D-mask effect

Jung-Hoon Ser, Tae-Hoon Park, Moon-Gyu Jeong, Eun-Mi Lee, Sung-Woo Lee, Chun-Suk Suh, Seong-Woon Choi, Chan-Hoon Park, Joo-Tae Moon

Proc. SPIE. 7640, Optical Microlithography XXIII

KEYWORDS: Semiconductors, Lithography, Electronics, Cadmium, Scanners, 3D modeling, Scanning electron microscopy, Photomasks, Optical proximity correction, Semiconducting wafers

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Showing 5 of 8 publications

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