All chipmakers understand that variability is the adversary of any process and reduction is essential to improving yield which translates to profit. Aggressive process window and yield specifications necessitate tight inline variation requirements on the DUV light source which impact scanner imaging performance. Improvements in reducing bandwidth variation have been realized with DynaPulse™ bandwidth control technology as significant reduction in bandwidth variation translates to a reduction in CD variation for critical device structures.
Previous work on a NAND Via layer has demonstrated an improvement in process capability through improve source and mask optimization with greater ILS and reduced MEEF that improved CDU by 25%. Using this Via layer, we have developed a methodology to quantify the contribution in an overall CDU budget breakdown. Data from the light source is collected using SmartPulse™ allowing for the development of additional methodologies using predictive models to quantify CD variation from Cymer’s legacy, DynaPulse 1 and DynaPulse 2 bandwidth control technologies. CD non-uniformities due to laser bandwidth variation for lot to lot, wafer to wafer, field to field and within field is now available based on known sensitivities and modeled. This data can assist in understanding the contribution from laser bandwidth variation in global and local CDU budgets.
Inverse lithography is increasingly being used as a viable OPC solution to maximize process window (PW), improve CD uniformity (CDU) and minimize the mask error factor (MEF), especially for memory devices. The device yield is typically limited by the process window of a few critical layers, and the Via layer is identified as one of the process window limiters for advanced 3D-NAND devices. To maximize the on-chip yield, ASML has developed advanced image based Mask-3D (M3D) inverse technology that can optimize freeform mask shapes and enhance design printability throughout the mask optimization flow. Mask rule checks (MRC) and side-lobe printing are optimized simultaneously to deliver the maximum process window.
The advanced image based M3D inverse lithography technology (ILT) is used to perform full chip mask correction on the Via layer of a 3D-NAND device. 3D NAND devices contain highly repetitive cell and page buffer patterns. To ensure the full chip device performance, the consistency of the mask correction is important. Our strategy is to use the computationally intensive mask optimization solution from the new advanced image based M3D inverse technology to generate a freeform mask which gives the best lithography performance. We then use Tachyon’s Pattern Recognition and Optimization (PRO) engine to propagate the freeform mask solution of the repetitive patterns to the full chip. The periphery of the chip is optimized using conventional OPC methods. The simulation results from the advanced image based M3D inverse technology are compared against the baseline flow, which uses a standard inverse solution. The simulation results from both the flows are further validated on wafer. Significant improvement in overlapping process window (OPW) and CD uniformity is observed using the new advanced inverse technology. The simulation data shows a 32% improvement in depth of focus (DOF), a 5% improvement in the image log slope (ILS) and a 25% reduction in best focus shift (BFS) range. The improvement has also been verified at the wafer-level.