Computational enablement for designs with sub-20nm metal tip to tip using cut shapes from grapho-epitaxy directed self-assembly
Electrical study of DSA shrink process and CD rectification effect at sub-60nm using EUV test vehicle
Design technology co-optimization assessment for directed self-assembly-based lithography: design for directed self-assembly or directed self-assembly for design?
Special Section Guest Editorial:Extending VLSI and Alternative Technology with Optical and Complementary Lithography
Directed self assembly on resist-limited guiding patterns for hole grapho-epitaxy: Can DSA help lower EUV's source power requirements?
Exploiting sub-20-nm complementary metal-oxide semiconductor technology challenges to design affordable systems-on-chip
Progress towards the integration of optical proximity correction and directed self-assembly of block copolymers with graphoepitaxy
Design and manufacturability tradeoffs in unidirectional and bidirectional standard cell layouts in 14 nm node
Fast source independent estimation of lithographic difficulty supporting large scale source optimization
Demonstrating the benefits of source-mask optimization and enabling technologies through experiment and simulations
A computational technique to optimally design in-situ diffractive elements: applications to projection lithography at the resist resolution limit
Experimental result and simulation analysis for the use of pixelated illumination from source mask optimization for 22nm logic lithography process
Methodology for generating exposure tool specifications for alternating phase-shift mask application for 70-nm node
Study of the impact to image quality and overlay by different pupil fills in a DUV scanner via overlay metrology
Etch integration issues in the development of deep submicron contacts utilizing DUV resist and organic BARC