In contrast to defect limited yield loss, systematic yield detractors like lithography hotspots may cause a huge yield loss
per event. For 45 nm and subsequent technology nodes, those findings are for this reason classified as DRC-like errors
and need to be fixed before tape-out. In this paper, we report a comparison - from the use-model point-of-view - of two
different methods for removal of lithography hotspots. First, a rip-up & re-routing and second, a guided-repair approach
will be presented. This includes a discussion of the impact in the routing context, mainly radius of influence and timing
closure, aspects of multiple layer involvement and the layout hierarchy, and the limitations caused by the layout grid.
Particle induced defects are still one of the major sources of yield loss in semiconductor manufacturing. In addition, optical distortion of shapes cannot be ignored in modern technologies and requires increasing design effort in order to avoid yield loss and minimize manufacturing costs. Although suppliers of automated routing tools are increasingly addressing these issues, we still see significant improvement potential even in layouts produced by routers attributed as DfM aware. We propose a post-routing clean-up step to address both defect and lithography related yield loss in the routing layers. In contrast to a "find and fix" approach, this methodology creates lithography friendly layout "by construction", based on the general concept of shape simplification and standardization.
With the upcoming technology generations, it will become increasingly challenging to provide a good yield and/or yield
ramp. In addition, we observe yield detractors migrating from defects via systematic effects such as litho and CMP to
out-of-spec scenarios, i.e. a slow, but continuous migration into an typical environment for analog devices. Preparing for
such scenarios, worldwide activities are ongoing to extract the device parameters not from the drawn layout, but from the
resist image or, at best, from etched contours. The litho-aware approach allows to detect devices of high variability and
to reduce the variations on the critical paths based on this analysis. We report in this paper the analysis of MOSFET
parameters from printed PC contours of standard cell libraries based on litho simulation (LfD). It will be shown how to
extract gate lengths and -widths from print images, how to backannotate the gate parameters into a litho-aware spice
netlist and to finally analyse the effect of across chip line width variations (ACLV) and process window influence based
on litho-aware spice netlist.
In the recent year tools for DFM (Design for Manufacturing) addressing the lithographic pattern transfer like LfD have
evolved besides OPC (Optical Proximity Correction) to reduce the time required from design to manufacturing along the
design to mask data preparation flow. The insertion of ORC (Optical Rule Check) after OPC in a separate mask data
preparation step has been commonly adopted in order to successfully meet the ever increasing need of an advanced
technology node like 130nm, 90nm, 65nm and below. Separate simulation runs are normally done for both OPC and
ORC and it is not unusual that different platforms (software, hardware or algorithm) are used for OPC and ORC,
especially for better ORC processing throughput. An investigation has been made to look into the possibility of a DFMlite
approach by inserting ORC into the OPC run on the same Calibre platform. This is accomplished by adding
additional intelligence necessary to provide a 'polishing' step for a hotspot identified, without increasing the combined
cycle time but having the benefit of both full OPC and partial ORC in a single simulation run.
Proc. SPIE. 6521, Design for Manufacturability through Design-Process Integration
KEYWORDS: Lithography, Calibration, 3D modeling, Scanning electron microscopy, Printing, Design for manufacturing, Semiconducting wafers, Prototyping, Process modeling, Resolution enhancement technologies
With the upcoming technology generations, it will become more and more challenging to provide a good yield and a
fast yield ramp. The contribution of Resolution Enhancement Technologies (RET) to Design for Manufacturability
(DfM) targets is to provide a good printability over the whole process window and the control by print image simulation
(PW-ORC) and to identify and remove yield issues imprinted in the drawn layout in early phases of the design flow.
Such a lithography-aware design data flow, which we call LfD (Litho-friendly Design) will be a very important step
towards a fully developed DfM environment.
We report in this paper the application of a LfD design flow used for library cells at the MAPLE, an Infineon 65 nm
design prototype fabricated by Chartered. The results of the process variability analysis are verified by experimental
results (dose-focus exposure matrices).
During the last years, various DfM (Design for Manufacturability) concepts have been proposed and discussed.
Resolution enhancement technologies with the goal to provide reasonable printability over the whole lithographic
process window, and the optimization of these tools and processes by print image simulation (PW-ORC) have become
crucial aspects of DfM today. In addition, designers and layouters will become increasingly involved in yield
discussions, as they will get tools and methods to identify and remove yield issues in the drawn layout. Such a
lithography-aware design data flow, which is called LfD (Litho-friendly Design), is a very important step towards a fully
developed DFM environment.
Recently, the leading EDA tool vendors have provided tools for efficient process window analysis and a scoring of
lithography issues in a form, which is close to productive usability. We report in this paper the implementation of LfD
into the design flow of library cells for the 90 nm and the 65 nm design rule technologies. Specific aspects of such a LfD
flow, like the availability of robust process models in early development stages are discussed as well as appropriate
means to assess the results.
The role the Optical Rule Check (ORC) in the design flow and future directions are discussed, the benefit of the model-based
methodology is illustrated by using realistic layout situations. Concepts for implementation of Litho-friendly
Design (LfD), i.e., of layout optimization and lithography simulations in the pre-tapeout design flow are developed.
From the early development phase up to the production phase, test pattern play a key role for microlithography. The requirement for test pattern is to represent the design well and to cover the space of all process conditions, e.g. to investigate the full process window and all other process parameters. This paper shows that the current state-of-the-art test pattern do not address these requirements sufficiently and makes suggestions for a better selection of test pattern. We present a new methodology to analyze an existing layout (e.g. logic library, test pattern or full chip) for critical layout situations which does not need precise process data. We call this method "process space decomposition", because it is aimed at decomposing the process impact to a layout feature into a sum of single independent contributions, the dimensions of the process space. This is a generalization of the classical process window, which examines defocus and exposure dependency of given test pattern, e.g. CD value of dense and isolated lines. In our process space we additionally define the dimensions resist effects, etch effects, mask error and misalignment, which describe the deviation of the printed silicon pattern from its target. We further extend it by the pattern space using a product based layout (library, full chip or synthetic test pattern). The criticality of pattern is defined by their deviation due to aerial image, their sensitivity to the respective dimension or several combinations of these. By exploring the process space for a given design, the method allows to find the most critical patterns independent of specific process parameters. The paper provides examples for different applications of the method: (1) selection of design oriented test pattern for lithography development (2) test pattern reduction in process characterization (3) verification/optimization of printability and performance of post processing procedures (like OPC) (4) creation of a sensitive process monitor.
The MueTec <M5k> advanced CD metrology and review station, operating at the DUV (248nm) wavelength, has been extensively characterised for a number of feature types relevant to advanced (9Onm technology node) reticles. Performance for resolution capability and measurement repeatability is presented here for chrome-on-glass feature types concentrating upon lines and spaces, contact holes and dots. The system has already demonstrated the ability to image 100nm Cr lines and sub-nanometre (3- sigma) long-term repeatability on lines and spaces down to 200nm in size. We will now show that this performance level can be achieved and sustained at production levels of throughput and under typical cleanroom environmental conditions. Performance of new software tools to support the advanced metrology of 90-nm node reticles will also be introduced and their performance evaluated. Comparison will be made between CD-SEM measurements and the advanced optical metrology offered by the <M5k> tool. Finally, reliability data for the tool —both in terms of mechanical and sustained repeatability performance — will be given, following prolonged trials in a production environment.
A comparison has been made in terms of mask CD linearity measurements between the 2 tool versions of a 248nm based optical CD metrology tool for photomasks, i.e., the high-NA M5k-SWD and the through-pellicle M5k-LWD, as well as to a reticle SEM, i.e., the KLA-T 8250-XR. The measured pattern consists of lines and dots (dark features), and spaces arid contact holes (clear features), both in equal-lines-and-spaces and as isolated feature. Two masks have been measured with the same test pattern, i.e., a binary and a 9%-attPSM for 193nm lithography. The latter was especially challenging because typically such embedded phase shift masks are much more transparent at higher wavelengths than those for which they are optimized. All measurements on the M5k were made intentionally before calibration (apart fmm pitch calibration). The resolution performance of the M5k-LWD and the measurement offsets found between M5k and SEM, as well as between the two M5k-versions is discussed. In addition, two-dimensional metrology based on feature contour extraction from optical or from SEM images has been compared. Although its resolution is inherently lower than that of the high-NA M5k-SWD and a reticle SEM, the M5k-LWD offers a possibility to extend such assessment to pelliclized reticles, which is not possible on the alternative tools.
The new MueTec <M5k>, an advanced CD metrology and review station operating at DUV (248nm) wavelength, has been extensively characterised in a reticle production environment. Performance data including resolution, measurement repeatability and throughput will be discussed. The system has demonstrated the ability to image 100nm Cr lines and sub-nanometer (3-sigma) long-term repeatability on lines and spaces down to 200nm in size. Metrology capability on contact hole and serif structures will also be discussed.
The paper will also introduce the application of a long working distance DUV objective compatible with pelliclised masks. With a 9% EAPSM reticle for 193nm wavelength a very appropriate image contrast was obtained with both objective types, allowing reliable automated linearity measurements on this type of reticle also.
In addition to the metrology performance of the tool, its integration into a manufacturing environment will also be described. This will show how the availability of networked co-ordinate data (either in the form of ASCII files or CATS data) and the high-accuracy stage of the tool enable efficient, automated measurement of large numbers of dense features under production conditions.
The reduction of wavelength in optical lithography and the use of enhancement techniques like phase shift technology, optical proximity correction (OPC), or off-axis illumination, lead to new specifications for advanced photomasks: a challenge for cost effective mask qualification. `Q-CAP', the Qualification Cluster for Advanced Photomasks, comprising different inspection tools (a photomask defect inspection station, a CD metrology system, a photomask review station and a stepper simulation software tool) was developed to face these new requirements. This paper will show the performance and reliability of quality assessment using the Q-CAP cluster tool for inspection and qualification of photomasks. Special attention is paid to a key issue of mask qualification: the impact of CD deviations, loss of pattern fidelity-- especially for OPC pattern and mask defects on wafer level.
The reduction of wavelength in optical lithography, phase shift technology and optical proximity correction (OPC), requires a rapid increase in cost effective qualification of photomasks. The knowledge about CD variation, loss of pattern fidelity especially for OPC pattern and mask defects concerning the impact on wafer level is becoming a key issue for mask quality assessment. As part of the European Community supported ESPRIT projection 'Q-CAP', a new cluster concept has been developed, which allows the combination of hardware tools as well as software tools via network communication. It is designed to be open for any tool manufacturer and mask hose. The bi-directional network access allows the exchange of all relevant mask data including grayscale images, measurement results, lithography parameters, defect coordinates, layout data, process data etc. and its storage to a SQL database. The system uses SEMI format descriptions as well as standard network hardware and software components for the client server communication. Each tool is used mainly to perform its specific application without using expensive time to perform optional analysis, but the availability of the database allows each component to share the full data ste gathered by all components. Therefore, the cluster can be considered as one single virtual tool. The paper shows the advantage of the cluster approach, the benefits of the tools linked together already, and a vision of a mask house in the near future.
The reduction of the wave length in the optical lithography in combination with mask enhancement techniques like phase shift pattern, optical proximity correction (OPC) or off- axis illumination requires a rapid increase in measurement accuracy and cost effective qualification of advanced photo masks. The knowledge about the impact of CD deviations, loss of pattern fidelity--especially of OPC structures--and mask defects on wafer level in more and more essential for mask qualification.