Scaling toward 65 nm and beyond, process variations are increased and influences both functional yield and parametric
yield. The process variations consist of systematic components and random components. Systematic variations are
caused by predictable design and process procedures, therefore systematic variations should be removed from process
corner model for LSI design. With the effect of scaling, print images on a wafer shows complicated distortion. The
method of calculating distorted transistor properties without slicing into individual rectangular transistors has been
previously proposed. Using this calculation method, transistor properties with distortion are able to be calculated,
reduction of transistor property variations is expected. Transistor property variations caused by layout dependence could
be reduced by using OPC with SPICE for each transistor, however, the calculation time of gate length retarget with
SPICE is not realistic. Therefore we have investigated approximation for transistor properties using statistics of gate
length distribution and layout parameters, and found that parameter fitting by average and &sgr; of gate length distribution
of each transistor is useful. According to the results of application to standard cell libraries using OPC with transistor
property estimation, we have achieved that our new OPC reduces threshold voltage and drive current variations greatly
without increasing throughput. It is difficult to suppress variation about all properties without area penalty, however,
property priority required for each transistor is different. Therefore performance improvement of the whole circuit and
chip is possible by the argument of priority between manufacturing engineer and circuit designer or using design intents.
At deep sub-wavelength nodes, it is difficult to transfer accurate mask pattern onto the wafer. However, actual gate pattern is distorted, and timing analysis tools calculates circuit performance on the assumption that the same gate length exists throughout the whole gate width. We calculated the property of the original 2 dimensional distorted transistor by using distribution of gate length. Firstly, in order to evaluate the accuracy of this approach, we have compared them with experimental results that may influence the 65 nm-node design rule. In the conventional method using a rectangular model, results of transistor properties are different from the experimental values, however, results of this approach can reproduce the experimental results. Secondly, this approach is applied to optimization of layout design and OPC. In order to investigate the influence of circuit performance on a layout design and OPC, we calculated the properties (drive current; Ion and leakage current; Ioff) of each transistor contained in standard cell library which is most referred to in a system LSI. We have investigated 2 layouts and 8 OPCs. According to these results, we find out that optimal OPC differs according to the prioritization of Ion and Ioff, whether it is an N-channel or P-channel, and also by layout. Furthermore relaxation of layout decreases variability of Ion caused by defocus. Moreover, since the influence of pattern distortion can be expressed by circuit term such as Ion and Ioff in addition to conventional process terms, it becomes easier for designers to understand manufacturing issues.
We examined two EPL mask fabrication processes to control precisely image placement (IP) on the EPL masks. One is a wafer process using an electrostatic chuck during an e-beam write and another is a membrane process using a mechanical chuck during the e-beam write. In the wafer process, the global IP is corrected during the e-beam write on the basis of the IP data taken with x-y metrology tool. In the membrane process, the global IP is corrected during the e-beam write on the basis of the data taken with the x-y metrology tool and taken in situ with the e-beam writer. The resist and final global IP (3s) of the wafer process is 7.2 nm and 10.6 nm. For the average local IP errors (3s), the local IP of 5.7 nm at the resist step increases to 14.7 nm at the final step due to process-induced distortions. The local IP could be reduced to 6.0 nm by applying the constant scale value to the mask process. In the membrane process, the resist and final global IP (3s) is 15.3 nm and 17.1 nm. With more detectable alignment marks, it would be possible to improve the global IP. For the average local IP errors (3s) of the membrane process, the average resist and final local IP are 6.7 and 7.1 nm which shows no PID. The two approaches proved to control IP more accurately than the conventional one.
Electron projection lithography (EPL) is one of the most promising candidates for the next generation lithography toward the hp 45 nm-node and beyond. EPL employs a stencil mask made from 200 mm Si wafer without a support frame, therefore chucking of an EPL tool and a metrology tool causes deformation in an EPL reticle. However, linear components of sub-field (SF) position error can be corrected by reticle alignment features of an EPL tool, whereas the non-linear components of SF position error can be corrected where each SF is measured beforehand and the corresponding reticle distortion correction (RDC) data is fed into the EPL exposure tool. In order to realize higher throughput, expanding SF to 4 mm-sq on reticle scale from the present 1 mm-sq is examined at the future EPL tool. For our studies we have investigated global image placement (IP), local IP, and pattern distortion of two kinds of EPL reticle. Currently we find the effect of mask IP on wafer scale is less than 9 nm, and we believe that in the near future the EPL mask IP target for the hp 45 nm-node could be realized for both of SF size.
Proc. SPIE. 5751, Emerging Lithographic Technologies IX
KEYWORDS: Metals, Transmission electron microscopy, Lithography, Scanners, Copper, Scanning electron microscopy, Resistance, Electron beam lithography, Overlay metrology, Chemical mechanical planarization
We evaluate electron projection lithography (EPL) performance for a via layer at 65-nm and 45-nm technology nodes through the fabrication of a via-chain test element group (TEG) using EPL/ArF mix-and-match (M&M) lithography. The via-chain is prepared by tow-layer metallization using a Cu/low-k single damascene process. Here, Metal 1 (M1) and Metal 2 (M2) are patterned by using an ArF scanner, and Via 1 (V1) is patterned by using an EPL exposure system. For the EPL performance evaluation at 65-nm technology node, we utilized transmission electron microscope (TEM) and confirmed that a 100-nm via-chain is successfully fabricated and a yield of 94% is achieved. For an EPL performance evaluation at 45-nm technology node, also by using TEM, we confirmed that fabrication of a 70-nm via-chain with reasonable quality is feasible although with a lower yield. For our next step we are planning to carry out an EPL performance at 32-nm technology node by printing a via layer and a metal layer using a corresponding via-chain TEG. Here, M1, V1 and M2 will be patterned by using the EPL exposure system. Although an EPL development at 32-nm technology node is still at its early stages, a via-hole resist pattern of 50 nm and a lines and spaces (L/S) resist pattern of 45 nm have almost been completed. These results suggest that EPL is quite promising for meeting the back-end-of-line (BEOL) process requirement for 65-nm, 45-nm and also for 32-nm technology nodes.
Electron projection lithography (EPL) is one of the most promising candidates for the next generation lithography toward the hp 45 nm-node and beyond. EPL employs a stencil mask made from 200 mm Si wafer without a support frame, therefore chucking of an EPL tool and a metrology tool causes deformation in an EPL reticle. However, linear components of sub-field (SF) position error can be corrected by reticle alignment features of an EPL tool, whereas the non-linear components of SF position error can be corrected where each SF is measured beforehand and the corresponding reticle distortion correction (RDC) data is fed into the EPL exposure tool. The SF position error can be viewed as inter-SF IP error where it can be affected by the repeatability of measurement and by the repeatability of distortions caused by the chucking of the measurement tool and the EPL tool. The other part of inter-SF IP comes from the residual that relates to global IP. Besides inter-SF IP, intra-SF IP can be divided into "local IP" and "pattern distribution". For our studies we have investigated the measurement repeatability of the metrology tool (Nikon XY-6i), distortion repeatabilities caused by the chucking of the metrology tool and the EPL tool (NSR-EB1A), global and local IPs, and pattern distortion. Currently we find the effect of mask IP on wafer scale is less than 9 nm, and we believe that in the near future the EPL mask IP target for the hp 45 nm-node could be realized.
The world’s first electron projection lithography (EPL) R&D exposure tool was installed at our laboratory in June 2003, and we have evaluated its basic performance. The most feasible introduction of EPL into ultra-large-scale integration (ULSI) is mix-and-match use with an optical tool for critical layers at the 65 nm technology node (TN) and beyond. Overlay is the most crucial issue in mix-and-match lithography, so we focused on overlay in this evaluation. We found that the overlay performance of the EPL tool in mix-and-match use is 48.0 nm in the X direction and 45.7nm in the Y direction. To clarify details of deteriorated overlay accuracy, we divided it into 7 factors, finding underlayer distortion to be about 15 nm, residual reticle distortion 5 nm, subfield (SF) distortion 15 nm, main-field (MF) distortion 20 nm, reticle alignment accuracy 15 nm, repeatability 25 nm, and exposure field distortion 25 nm. We also demonstrated that overlay accuracy was 30 nm using previous overlay data.
Electron projection lithography (EPL) is a potential candidate for next-generation lithography (NGL) at the 65 nm technology node and beyond. EPL presents two key issues influencing design, because EPL uses EB and a stencil mask: beam blur and mask image placement (IP). Beam-blur deterioration depends on the Coulomb effect and is proportional to the beam current on the wafer, which depends on pattern density and the beam current on the mask. Pattern density in each subfield (SF) must be limited if the beam current on the mask is decided from throughput. IP accuracy of the stencil mask depends on the pattern layout. Intrinsic stress vanishes at openings, and distorted stress distribution causes IP error. To determine the influence of pattern layout on mask IP accuracy, simulation is checked in two steps. In the first step, simulation calculates the correlation between maximum displacement and pattern density in the entire SF. In the second step, simulation calculates the correlation between the side length of local area L and maximum additional displacement. The result of the first simulation shows that pattern deformation depends on the difference between half of the SF’s patterns density difference. To estimate the influence of pattern density imbalance in an area smaller than half of the SF, additional deformation of local area (L x L) is calculated in the second simulation step. Maximum additional displacement increases with L and pattern density. Based on the correlation between beam blur and pattern density and simulations results, the design rule (DR) for EPL is defined as the maximum pattern density in each entire SF and local area (L x L).
Electron projection lithography (EPL) is a promising candidate for next-generation lithography (NGL) at the 65 nm technology node and beyond. Nikon has developed the world's first full-field EPL exposure tool, Nikon's NSR-EB1A. This tool was shipped to Selete in June 2003. Final installation is still in progress, but we have begun evaluating its applicability to the 65 nm technology node through trial fabrication of a test element group (TEG). A TEG of via-hole chains consisting of 1st metal, 1st via, and 2nd metal layers was fabricated using optical/EPL mix-and-match lithography.
We applied EPL to the via layer. The purpose of the first fabrication is to clarify practical hole resolution of the EPL tool because EPL is expected to define finer hole patterns and enable denser integration than optical lithography. To prevent defects in metal layers from adversely affecting evaluation, we used moderate pattern layouts in metal layers. Metal layers were defined by an ArF scanner to obtain good pattern fidelity and sufficient pattern yield. We used a single damascene process with a low-k insulator and Cu interconnection. Practical hole resolution was evaluated by electrical measurement and SEM and TEM observation. SEM confirmed that via holes of 70 nm were resolved. TEM confirmed that via-hole chains of 80 nm were fabricated. Electrical measurement confirmed electrical conduction through via-hole chains of 75 nm. These results suggest that applying EPL to hole layers could realize denser integration than optical lithography. EPL application to TEG trial fabrication demonstrates its high-resolution capability in practical use.
EPL (Electron Projection Lithography) is one of viable candidates for the NGL (Next Generation Lithography) used for the 65nm technology node and below. EPL uses the membrane mask with grillage structure to reinforce the membrane area. The NGL poses stringent requirements to mask accuracy. The most severe problem of membrane mask is IP (Image Placement) accuracy. In this study, distortion characteristics of an EPL stencil mask are analyzed by FEM (Finite Element Method). Its dependence on the grillage structure and the distribution of pattern density is presented. The distortion of the wet-etched wide grillage is negligible compared to the required IP accuracy. However, the distortion of the dry-etched narrow grillage cannot be negligible, which exceeds 5nm. The accumulation of the distortion will deteriorate the IP accuracy. The non-uniform distribution causes much larger distortion in membrane than the uniform one, which is quite unacceptable for the 65nm technology node and below. Improvement of the IP accuracy by the correction using an EPL optical system is also evaluated. The EPL optical system can reduce the distortion caused by the uniform distribution. However, the large distortion caused by the non-uniform distribution cannot be corrected. EPL requires its own design rules regulating the distribution of pattern density from the view point of IP accuracy.
In order to solve the various problems associated with a LEEPL mask as originally demonstrated in the form of single-membrane diamond mask, we propose a new mask format termed COSMOS (complementary stencil mask on strut-supports). The COSMOS has small-area membranes with strut reinforcement and is somewhat similar to the masks used for other types of electron projection lithography (EPL). However, the exposure strategy is completely different from the other EPLs; a complete pattern image can be transcribed by overlaying complementary portions of a mask pattern via multiple exposures. The inter-membrane and intra-membrane distortions of image placement have been computed by the finite element method (FEM) simulation. It is concluded that the global distortion induced by the inversion of gravity can be corrected for by mask writing, and the intra-membrane distortion, induced by both the gravitational flexure of a membrane and the pattern density distribution, can be neglected with the membrane intrinsic stress of approximately 5 Mpa..
The technological systematics for low-energy electron-beam proximity-projection lithography (LEEPL) is discussed with particular focuses on the key ingredients such as mask, resist and alignment. We have developed a mechanically rigid 1X stencil mask supported by a grid-work of struts, high-resolution chemically-amplified resists to be used for multi layer processes, and the accurate alignment method to overlay complementary split patterns. The LEEPL beta machine as combined with these techniques was successfully used to demonstrate its imaging capability for the 70 nm node.