Plasma etch challenges such as resolution enhancement, etch error reduction, and process reliability improvement are investigated in next generation phase shift photomask processes for ≤14nm technology node. Etch resolution predominantly depends on etch bias and linearity while overall process resolution is also determined by resist thickness. Several resolution enhancement techniques including thin hardmasks and new absorber materials are tested in terms of etch profile, linearity, and minimum feature printability. New approaches provide improvement on etch bias as well as good pattern fidelity for sub-resolution patterns. Reduction of etch profile errors is also critical to maintain high pattern resolution. It is found that some of etch profile distortion can be minimized by changing plasma conditions. To
meet tighter process reliability requirement, we investigated a couple of advanced process control techniques in alternating phase shift mask manufacturing. Integration of real-time monitor is essential to obtain good process reliability with no degradation on defects or throughput.
Pixelated phase masks rendered from computational lithography techniques demand one generation-ahead mask
technology development. In this paper, we reveal the accomplishment of fabricating Cr-less, full field, defect-free
pixilated phase masks, including integration of tapeout, front-end patterning and backend defect inspection, repair,
disposition and clean. This work was part of a comprehensive program within Intel which demonstrated microprocessor
To pattern mask pixels with lateral sizes <100nm and vertical depth of 170nm, tapeout data management, ebeam write
time management, aggressive pattern resolution scaling, etch improvement, new tool insertion and process integration
were co-optimized to ensure good linearity of lateral, vertical dimensions and sidewall angle of glass pixels of arbitrary
pixelated layout, including singlets, doublets, triplets, touch-corners and larger scale features of structural tones
including pit/trench and pillar/mesa. The final residual systematic mask patterning imperfections were corrected and
integrated upstream in the optical model and design layout.
The volume of 100nm phase pixels on a full field reticle is on the order tera-scale magnitude. Multiple breakthroughs in
backend mask technology were required to achieve a defect free full field mask. Specifically, integration of aerial
image-based defect inspection, 3D optical model-based high resolution ebeam repair and disposition were introduced.
Significant reduction of pixel mask specific defect modes, such as electro static discharge and glass pattern collapse,
were executed to drive defect level down to single digit before attempt of repair. The defect printability and repair yield
were verified downstream through silicon wafer print test to validate defect free mask performance.
This work describes the advantages, tolerances and integration issues of using Pixelated Phase Masks for patterning
logic interconnect layers. Pixelated Phase Masks (PPMs) can act as variable high-transmission attenuated phase shift
masks where the pixelated phase configuration simultaneously optimizes OPC and SRAF generation. Thick mask
effects help enable PPMs by allowing larger minimum pixel sizes and phase designs with near equal sized zero and piphase
regions. PPMs with a 3-tone pixel mask (un-etched glass, etched glass, chrome) offer more flexible patterning
capability compared to 2-tone pixel mask (no chrome) style but at the detriment of a more complex mask making
process. We describe the issues and opportunities associated with using PPMs for patterning a 65nm generation first
level metal layer of a micro-processor.
As mask feature size decreases, etch bias control during Cr and shifter etch becomes more critical factor in Embedded
Phase Shifter Mask (EPSM) mask making processes. Since the etching characteristics of the shifter materials,
Molybdenum Silicide (MoSi), are sensitive to etching surface condition, Critical Dimension (CD) performance of the
shifter layer strongly depends on incoming surface condition from Cr etch. In this paper, lateral etch component of MoSi
etch was investigated as a function of various substrate conditions so that a new in-situ plasma treatment was suggested
to control the CD bias during MoSi etch. The CD performance was characterized within the surface treatment plasmas
and also correlated with some plasma parameters and substrate temperature. As a result, it was found that plasma surface
modification could be an in-situ technique to better control the shifter CD in EPSM process and an essential option for
redundancy tools in mask production environment.
As mask pattern feature sizes shrink the need for tighter control of factors affecting critical dimensions (CD) increases
at all steps in the mask manufacturing process. To support this requirement Intel Mask Operation is expanding its
process and equipment monitoring capability. We intend to better understand the factors affecting the process and
enhance our ability to predict reticle health and critical dimension performance.
This paper describes a methodology by which one can predict the contribution of the dry etch process equipment to
overall CD performance. We describe the architecture used to collect critical process related information from various
sources both internal and external to the process equipment and environment. In addition we discuss the method used to
assess the significance of each parameter and to construct the statistical model used to generate the predictions. We
further discuss the methodology used to turn this model into a functioning real time prediction of critical dimension
performance. Further, these predictions will be used to modify the manufacturing decision support system to provide
early detection for process excursion.
Alternating Phase Shift Mask (APSM) Technology has been developed and successfully implemented for the poly gate of 65nm node Logic application at Intel. This paper discusses the optimization of the mask design rules and fabrication process in order to enable high volume manufacturability. Intel's APSM technology is based on a dual sided trenched architecture. To meet the stringent OPC requirements associated with patterning of narrow gates required for the 65nm node, Chrome width between the Zero and Pi aperture need to be minimized. Additionally, APSM lithography has an inherently low MEEF that furthermore, drives a narrower Chrome line as compared to the Binary approach. The double sided trenched structure with narrow Chrome lines are mechanically vulnerable and prone to damage when exposed to conventional mask processing steps. Therefore, new processing approaches were developed to minimize the damage to the patterned mask features. For example, cleaning processes were optimized to minimize Chrome & quartz damage while retaining the cleaning effectiveness. In addition, mask design rules were developed which ensured manufacturability. The narrow Chrome regions between the zero and Pi apertures severely restrict the tolerance for the placement of the second level resists edges with respect to the first level. UV Laser Writer based resist patterning capability, capable of providing the required Overlay tolerance, was developed, An AIMS based methodology was used to optimize the undercut and minimize the aerial image CD difference between the Zero and Pi apertures.