We have been researching new mask blank materials for the next generation lithography (NGL) and developed
a new mask blank with low-k phase shifter  . The low-k phase shifter consists of only Si and N. In our previous
work, we reported the advantages of developed SiN phase shift mask (PSM) . It showed high lithographic
performance and high durability against ArF excimer laser as well as against cleaning. In this report, we further verified
its high lithographic performance on several types of device pattern. The SiN PSM had high lithographic performance
compared with conventional 6% MoSi PSM. Exposure latitude (EL) and mask enhancement factor (MEEF) were
especially improved on originally designed Gate, Metal and Via patterns.
The 1Xnm technology node lithography is using SMO-ILT, NTD or more complex pattern. Therefore in mask defect inspection, defect verification becomes more difficult because many nuisance defects are detected in aggressive mask feature. One key Technology of mask manufacture is defect verification to use aerial image simulator or other printability simulation. AIMS™ Technology is excellent correlation for the wafer and standards tool for defect verification however it is difficult for verification over hundred numbers or more. <p> </p>We reported capability of defect verification based on lithography simulation with a SEM system that architecture and software is excellent correlation for simple line and space. <p> </p>In this paper, we use a SEM system for the next generation combined with a lithography simulation tool for SMO-ILT, NTD and other complex pattern lithography. Furthermore we will use three dimension (3D) lithography simulation based on Multi Vision Metrology SEM system. Finally, we will confirm the performance of the 2D and 3D lithography simulation based on SEM system for a photomask verification.
In a Photomask manufacturing process, mask defect inspection is an increasingly important topic for 193nm optical lithography. Further extension of 193nm optical lithography to the next technology nodes, staying at a maximum numerical aperture (NA) of 1.35, pushes lithography to its utmost limits. This extension from technologies like ILT and SMO requires more complex mask patterns. In mask defect inspection, defect verification becomes more difficult because many nuisance defects are detected in aggressive mask features. One of the solutions is lithography simulation like AIMS. An issue with AIMS, however, is the low throughput of measurement, analysis etc.
The retardation of the development of NGL techniques causes the extension of ArF immersion lithography for 1x-nm node. We have been researching the new phase shift mask's (PSM) material for the next generation ArF lithography. In this reports, we developed the low-k, high transmission PSM and evaluate it. The developed new PSM shows good lithographic performance in wafer and high ArF excimer laser durability. The mask processability were confirmed such as the CD performance, the cross section image, the inspection sensitivity and repair accuracy.
In this report, we compared the lithographic performances between the conventional positive tone development (PTD) process and the negative tone development (NTD) process, using the lithography simulation. We selected the MoSi-binary mask and conventional 6% attenuated phase shift mask as mask materials. The lithographic performance was evaluated and compared after applying the optical proximity correction (OPC). The evaluation items of lithographic performance were the aerial image profile, the aerial image contrast, normalized image log slope (NILS), mask error enhancement factor (MEEF), and the bossung curves, etc. The designs for the evaluation were selected the simple contact hole and the metal layer sample design.
AIMS<sup>™</sup> is mainly used in photomask industry for verifying the impact of mask defects on wafer CD in DUV lithography process. AIMS verification is used for D2D configuration, where two AIMS images, reference and defect, are captured and compared. Criticality of defects is identified using a number of criteria. As photomasks with aggressive OPC and sub-resolution assist features (SRAFs) are manufactured in production environment, it is required to save time for identifying reference pattern and capturing the AIMS image from the mask. If it is a single die mask, such technology is truly not applicable. A solution is to use AIMS die-to-database (D2DB) methodology which compares AIMS defect image with simulated reference image from mask design data. In general, simulation needs calibration with AIMS images. Because there is the difference between an AIMS image except a defect and a reference image, the difference must be compensated. When it is successfully compensated, AIMS D2DB doesn’t need any reference images, but requires some AIMS images for calibration. Our approach to AIMS D2DB without calibration image is systematic comparison of several AIMS images and to fix optical condition parameters for reducing calibration time. And we tried to calibrate using defect AIMS image to this approach. In this paper, we discuss performance of AIMS D2DB simulation without calibration images.
In this study, we investigate what kind of mask blank material is optimum for the resolution
enhancement techniques (RET) of leading-edge ArF lithography. The source mask optimization (SMO) is
one of the promising RET in 2Xnm-node and it optimizes mask pattern and illumination intensity
distribution simultaneously. We combine SMO with the blank material optimization and explore the truly
This study consists of three phases. In the first phase, we evaluate maximum exposure latitude
(Max.E.L.) and mask error enhancement factor (MEEF) of fictitious materials that have typical real (n)
and imaginary (k) value of refractive index by 3D rigorous simulator as the basic analysis. The simulation
result shows that there are two high lithographic performance combinations of n and k values; one is
low-n/high-k and the other is high-n/low-k.
In the second phase, we select actual blank material that has similar optical parameters with the
result of the previous phase. The lithographic performance of the selected material is investigated more
precisely. We find that the candidate material has good lithographic performance at the semi-dense pitch.
In the final phase, we create a test mask of this candidate blank material and verify simulation
result by experimental assessment. The exposures are performed on NA1.30 immersion scanner (Nikon
NSR-S610C). The experimental result shows the improvement of Max.E.L. in head to head type pattern.
This study will discuss the potential of blank material tuning for the ArF lithography extension.
To improve lithography performance, resolution enhancement technique (RET) such as source mask
optimization (SMO) will be applied to 22 nm node and beyond. We examine if lithography performance is improved
by altering mask 3D topography. In this paper, we report that we have confirmed what topography is effective for
lithography performance improvement in the dense region of 22nm technology node. Since shadowing effect is
strong at the dense region, we focus on sidewall angle that decreases shadowing effect. As a basic analysis, we
evaluate maximum exposure latitude (EL) and mask error enhancement factor (MEEF) of mask 3D topographic
patterns that have various sidewall angles by 3D rigorous simulator. This result shows the increasing of maximum
exposure latitude when changing sidewall angle. As a next step, we fabricate a test mask which has optimized
sidewall angle and the exposure is performed on NA1.30 immersion scanner (Nikon NSR-S610C). Then we compare
wafer printing results and simulation results. These results induce that the optimization of mask 3D topography has a
potential to improve lithographic performance.
This paper tries to clarify the requirements for Source-Mask co-Optimization (SMO) type complex masks for low k<sub>1</sub>
technology nodes using a dedicated test mask. The current status of mask CD requirements and inspection capability for
Free Form (FF) SRAFs which give wider process window are discussed by comparing with Rectangular Shape (RS)
SRAFs. From CD deviation analysis with CD bias change at both main and SRAF patterns, the importance of CD
control at entire SRAF is emphasized although the partial lack of SRAF seems to give less impact on the main pattern
lithography performance. It is also suggested that SRAF printability of FF-SRAF needs to be carefully controlled with
mask bias error consideration. To identify the defects which give impact on litho performance, simulation-based defect
printability prediction (M-LMC) using inspection images is evaluated and found to be an important enabler for complex
mask inspection. The simulation-image based defect analysis helps to reduce the nuisance defects, and greatly saves
analysis time of measurement on Aerial Image Measurement System (AIMS<sup>TM</sup>). To introduce the complex free form
mask into production, mask-writing shot-count reduction is also evaluated. It is shown that fragmentation using Model-
Based (MB) Mask Data Preparation (MDP) effectively reduces the mask writing shot counts with using overlapping of
OPC technique is getting more complicated toward 32nm and below technology node, i.e. from moderate
OPC to aggressive OPC. Also, various types of phase shift mask have been introduced, and then the
manufacturing process of them is complicated now. In order to shorten TAT (Turn around time) time, mask
technique need be considered in addition to lithography technique.
Furthermore, the lens aberration of the exposure system is getting smaller, so the current performance of it is
very close to the ideal. On the other hand, when down sizing goes down to 32nm technology node, it starts to
be reported that there are cases that size cannot be matched between a mask pattern and the corresponding
printed pattern. Therefore, it is very indispensable to understand the pattern sizes correlation between a mask
and the corresponding printed wafer in order to improve the accuracy and the quality, in the situation that the
device size is so small that low k1 lithography had been developed and widely used in a production.
Then it is thought that it is one of the approaches to improve an estimated accuracy of lithography by using
contour that was extracted from mask SEM image in addition to mask model.
This paper describes a newly developed integration system in order to solve issues above, and the applications.
This is a system which integrates CG4500; CD-SEM for mask and CG4000; CD SEM for wafer; using
DesignGauge; OPC evaluation system by Hitachi High-Technologies.
It was investigated that a measurement accuracy improvement by executing a mask-wafer same point
measurement with same measurement algorithm utilizing the new system. At first, we measured patterns
described on a mask and verified the validity based on a measurement value, picture, measurement parameter
and the coordinate. Then create a job file for a wafer CD-SEM using the system so as to measure the same
patterns that were exposed using the mask. In addition, average CD measurement was tried in order to
improve the correlation. Also, in order to estimate very accurate pattern shape, a contour was calculated from a mask SEM image, the
result and the design data was used in a litho simulation. This realizes verification including mask error.
It is thought that it is beneficial for both mask maker and device maker to use this system.
OPC (Optical Proximity Correction) technique is getting more complicated towards 32 nm technology node and beyond,
i.e. from moderate OPC to aggressive OPC. Also, various types of phase shift mask have been introduced, and their
manufacturing process is complicated. In order to shorten TAT (Turn around time), mask design technique needs be
considered in addition to lithography technique.
Furthermore, the lens aberration of the exposure system is getting smaller, so its current performance is very close to the
ideal. On the other hand, when down sizing of device feature size reaches the 32nm technology node, cases begin to be
reported where the feature dimension is not matched between a mask pattern and the corresponding printed pattern.
Therefore, it is indispensable to understand the pattern size correlation between a mask and the corresponding printed
wafer in order to improve the processing accuracy and the quality in the situation where the device size is so small that
the low k1 lithography is widely used in production.
One of the approaches to improve the estimated accuracy of lithography is the use of contour data extracted from mask
SEM image in addition to the application of a mask model.
This paper describes a newly developed integration system that aims to solve the issues above, and its applications. This
is a system that integrates mask CD-SEM (Critical Dimension-Scanning Electron Microscope) CG4500, wafer CD-SEM
CG4000, OPC evaluation system DesignGauge, all manufactured by Hitachi High-Technologies.
The measurement accuracy improvement was examined by executing a mask-wafer same point measurement, i.e.
measurement of the corresponding points, with same measurement algorithm utilizing the new system. First, we
measured mask patterns and verified the validity based on the measurement value, the image, the measurement
parameter and the coordinates. Then a job file was formulated for a wafer CD-SEM using the new system so as to
measure the corresponding patterns that were exposed using the mask. In addition, the average CD measurement was
tried in order to improve the capability.
Furthermore, in order to estimate the pattern shape with high accuracy, a contour was calculated from a mask SEM
image, and the result was used with the design data in a litho simulation. This realizes a verification that includes mask
This system is expected to be beneficial for both mask makers and device makers.
In the continuous battle to improve critical dimension (CD) uniformity, especially for 45-nanometer (nm) logic
advanced products, one important recent advance is the ability to accurately predict the mask CD uniformity
contribution to the overall global wafer CD error budget. In most wafer process simulation models, mask error
contribution is embedded in the optical and/or resist models. We have separated the mask effects, however, by
creating a short-range mask process model (MPM) for each unique mask process and a long-range CD
uniformity mask bias map (MBM) for each individual mask. By establishing a mask bias map, we are able to
incorporate the mask CD uniformity signature into our modelling simulations and measure the effects on global
wafer CD uniformity and hotspots. We also have examined several ways of proving the efficiency of this
approach, including the analysis of OPC hot spot signatures with and without the mask bias map (see Figure 1)
and by comparing the precision of the model contour prediction to wafer SEM images. In this paper we will
show the different steps of mask bias map generation and use for advanced 45nm logic node layers, along with
the current results of this new dynamic application to improve hot spot verification through Brion Technologies'
model-based mask verification loop.
As the pattern feature sizes become smaller, photomask assurance by one-dimensional criteria using a CD-SEM is reaching its limits. For instance, minute steps generated by OPC (Optical Proximity Correction), especially under the influence of corner rounding, are hard to measure. Thus, photomask assurance by means of two-dimensional features has been studied.
Conventionally, in simulations to predict the printed shape on the wafer, OPCed data pattern have been used. While the OPCed data pattern represents the ideal pattern fidelity, actual pattern on a real photomask is different from the ideal shape. In addition, the increase of MEEF (Mask Error Enhancement Factor), along with the fine-than-ever pattern feature size, emphasizes the difference between the simulation result and the actually printed result on the wafer. To realize the two-dimensional assurance, we have to think of a method to predict the wafer image accurately. This is also important when we have to verify and manage the lithographic hotspots.
For this purpose, we have been studying a mask model, a technique to take into consideration the actual pattern fidelity on the photomask, by modeling mask patterns' linearity, proximity, corner-rounding, etc., for each mask making process. By applying the mask model to OPCed design pattern, mask pattern shapes were found to be accurately predicted before mask making.
Furthermore, we studied hotspot verification flow using the mask model. By the application of the mask model on the data pattern for the optical simulation, we accurately predicted the shape printed on the wafer, and accurately verify hotspots. This is expected to lead to assurance of photomask using two-dimensional shape.
One of the most critical points for accurate OPC is to have accurate models that properly simulate the full process from
the mask fractured data to the etched remaining structures on the wafer. In advanced technology nodes, the CD error
budget becomes so tight that it is becoming critical to improve modeling accuracy. Current technology models used for
OPC generation and verification are mostly composed of an optical model, a resist model and sometimes an etch model.
The mask contribution is nominally accounted for in the optical and resist portions of these models. Mask processing
has become ever more complex throughout the years so properly modeling this portion of the process has the potential
to improve the overall modeling accuracy. Also, measuring and tracking individual mask parameters such as CD bias
can potentially improve wafer yields by detecting hotspots caused by individual mask characteristics. In this paper, we
will show results of a new approach that incorporates mask process modeling. We will also show results of testing a
new dynamic mask bias application used during OPC verification.