The rapid advancement in lithography and continuing shrink in feature dimensions demand tighter overlay tolerances for
fabrication of memory circuits with higher yields (Refer to table 1 for ITRS overlay requirements). To meet tight overlay
tolerances, sources of alignment errors need to be identified and corrected accurately. Alignment errors can be
contributed by 3 factors; wafer induced shift (WIS), tool induced shift (TIS) and WIS-TIS interaction. WIS is introduced
by wafer processing while TIS is introduced by the alignment tool (i.e. scanner or metrology).
This paper introduces methods for improvement of alignment performance at layers that experience WIS. A study on
mark reflectivity was done. A number of various alignment mark designs were evaluated. The most robust mark to
Tungsten Chemical Mechanical Polishing (WCMP) process, based on experimental results, will be illustrated. The
concept of the 'Alignment Parameter Optimizer' to select the best alignment illumination mode for each mark and the
best sample shots for alignment within the wafer, taking throughput into consideration, will be discussed. A new
alignment algorithm that is able to compensate for asymmetric alignment marks will also be presented in this paper.
Finally, production data from a Dynamic Random Access Memory (DRAM) manufacturer with the implementation of
the above-mentioned concepts will be illustrated.