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As plasma etching is known to reduce line edge roughness on 193nm lithography printed features [2], we investigate in this paper the level of roughness that can be achieved on EUV photoresist exposed at a lower dose through etch process optimization into a typical back end of line film stack. We will study 16nm lines printed at 32 and 34nm pitch. MOX and CAR photoresist performance will be compared. We will review step by step etch chemistry development to reach adequate selectivity and roughness reduction to successfully pattern the target layer.
In this work, we highlight one contributor that may negatively impact the on-product overlay performance, namely the etch step. The focus will be mainly on the wafer edge region but the remaining part of the wafer is considered as well. Three use-cases are examined: multiple Litho-Etch steps (LEn), contact hole layer etch, and the copper dual damascene etch. We characterize the etch contribution by considering the overlay measurement after resist development inspect (ADI) and after etch inspect (AEI). We show that the Yieldstar diffraction based overlay (μDBO) measurements can be utilized to characterize the etch contribution to the overlay budget. The effects of target asymmetry as well as overlay shifts are considered and compared with SEM measurements.
Based on the results above, we propose a control solution aiming to reduce or even eliminate the delta between ADI and AEI. By doing so, target/mark to device offsets due to etch might be avoided.
Co-optimization of the lithography and etch processing is expected to be required to achieve the best pitch walk control. Previous work has shown that improving the across wafer CD uniformity of the line patterns after core etch has limited impact on the space CD uniformity after the SADP process, whereas the CD uniformity of the spaces after SAQP did show some dependence. There are additional space populations created by an SAQP process. The variation of these different populations, along with the spacer deposited line populations, is the root cause of the non-uniform grating that results in pitch walk. The complex interactions of the lithography and etch processes’ impact on the CD and profile need to be understood to produce the optimal performance.
Pitch walk is a component of the overall Edge Placement Error (EPE) budget. With current nodes using SAQP for multiple device layers and future nodes expected to continue to implement this patterning technique, minimization of pitch walk variability is an important part of overall patterning optimizations. In this work, we will show how cooptimized exposure dose and etch processes for SAQP patterning can improve pitch walk performance. We will provide a target exposure dose metric for a 32nm pitch SAQP grating. The methodology for achieving the best pitch walk performance by combination of etch process optimization with dose correction will also be shown.
To meet the scaling requirements and keep process complexity to a minimum, EUV is increasingly seen as the platform for delivering the exposures for both the grating and the cut/block patterns beyond N7. In this work, we evaluated the overlay and pattern fidelity of an EUV block printed in a negative tone resist on an ArF-i SAQP grating. High-order Overlay modeling and corrections during the exposure can reduce overlay error after development, a significant component of the total EPE. During etch, additional degrees of freedom are available to improve the pattern placement error in single layer processes.
Process control of advanced pitch nanoscale-multi-patterning techniques as described above is exceedingly complicated in a high volume manufacturing environment. Incorporating potential patterning optimizations into both design and HVM controls for the lithography process is expected to bring a combined benefit over individual optimizations. In this work we will show the EPE performance improvement for a 32nm pitch SAQP + block patterned Metal 2 layer by cooptimizing the lithography and etch processes. Recommendations for further improvements and alternative processes will be given.
In this paper we highlight the unique challenges associated in developing resist trim / reformation plasma etch process for SAQP integration scheme and summarize our efforts in optimizing the trim etch chemistries, process steps and plasma etch parameters for meeting the mandrel definition targets. Finally, we have shown successful patterning of 30nm pitch patterns via the resist-mandrel SAQP scheme and its implementation for Si-fin formation at 7nm node.
In this paper, we will demonstrate the role of the dual-frequency Capacitively Coupled Plasma (CCP) in the EUV patterning process with regards to improving LER/LWR, resist selectivity and CD tunability for holes and line patterns. One of the key knobs utilized here to improve LER and LWR, involves superimposing a negative DC voltage in RF plasma at one of the electrodes. The emission of ballistic electrons, in concert with the plasma chemistry, has shown to improve LER and LWR. Results from this study along with traditional plasma curing methods will be presented. In addition to this challenge, it is important to understand the parameters needed to influence CD tunability and improve resist selectivity. Data will be presented from a systematic study that shows the role of various plasma etch parameters that influence the key patterning metrics of CD, resist selectivity and LER/LWR. This work was performed by the Research Alliance Teams at various IBM Research and Development Facilities.
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