We have created a model that uses discriminant function analysis to predict failures in etched hole patterning of the type
that induces an open-contact failure by using critical dimension scanning electron microscope (CDSEM) measurement
values of after-development resist hole patterning. The input variables of the best model were found to be the resist hole
CD, the difference in resist hole CD between that of the 50% secondary electron (SE) threshold and that of the 20% SE
threshold, and ellipticity. The model indicates that a tapered resist profile is one of the main causes of the open-contact
failure in etched hole patterning. The model is applicable not only to lithography process optimization but also to
lithography process control, where the focus center of optical exposure at resist patterning is determined not only from
the perspective of resist CD but also from the perspective of suppressing the failures of etched hole patterning.
Below 40nm design node, systematic variation due to lithography must be taken into consideration during
the early stage of design.
So far, litho-aware design using lithography simulation models has been widely applied to assure that
designs are printed on silicon without any error.
However, the lithography simulation approach is very time consuming, and under time-to-market pressure,
repetitive redesign by this approach may result in the missing of the market window.
This paper proposes a fast hotspot detection support method by flexible and intelligent vision system image
pattern recognition based on Higher-Order Local Autocorrelation.
Our method learns the geometrical properties of the given design data without any defects as normal
patterns, and automatically detects the design patterns with hotspots from the test data as abnormal patterns.
The Higher-Order Local Autocorrelation method can extract features from the graphic image of design
pattern, and computational cost of the extraction is constant regardless of the number of design pattern
This approach can reduce turnaround time (TAT) dramatically only on 1CPU, compared with the
conventional simulation-based approach, and by distributed processing, this has proven to deliver linear
scalability with each additional CPU.
Resist process challenges for 32-nm node and beyond are discussed in this paper. For line and space (L/S) logic patterns,
we examine ways to balance the requirements of resolution-enhancement techniques (RETs). In 32-nm node logic
patterning, two-dimensional (2D) layout pattern deformation becomes more severe with stronger RET (e.g., narrow
angle CQUAD illumination). Also pattern collapse more frequently happens in 2D-pattern layouts when stronger RET is
used. In contrast, milder RET (annular illumination) does not induce the severe pattern collapse in 2D-pattern layout. For
2D-pattern layouts, stronger RET seems to worsen image contrast and results in high background-light in the resist
pattern, which induces more pattern collapse. For the minimum-pitch L/S pattern in 32-nm node logic, annular
illumination is acceptable for patterning with NA1.35 scanner when high contrast resist is used. For contact/via patterns,
it is necessary to expand the overlapping CD process window. Better process margin is realized through the combination
of hole-shrink technique and precise acid-diffusion control in an ArF chemically amplified resist.
We have designed the lithography process for 28nm node logic devices using 1.35NA scanner. In the
28nm node, we face on the ultra-low k1 lithography in which dense pattern is affected by the mask
topography effect and the oblique-incidence. Using the rigorous lithography simulation considering
the electro-magnetic field, we have estimated accurately the feasibility of resolution of the minimum
pitch required in 28nm node. The optimum mask plate and illumination conditions have been
decided by simulation. The experimental results for 28nm node show that the minimum pitch
patterns and minimum SRAM cell are clearly resolved by single exposure.
We have developed the lithography process for 32nm node logic devices under the 1.35NA single-exposure conditions. In low-k1 generation, we have to consider the minimum pitch resolution and two-dimensional pattern fidelity at the same time. Although strong RET (Resonance Enhancement Technique) can achieve the high image contrast, it has negative effects like line end shortening and resist pattern collapse. Moderate RET such as annular illumination can combine the minimum pitch resolution and two-dimensional pattern fidelity with hyper NA illumination condition. The simulation and experimental results indicate that the minimum pitches should be determined as 100nm for line pattern and 110nm for contact hole pattern, respectively. The isolated contact hole needs SRAF and focus drift exposure to improve DOF. Embedded SRAM cell of 0.125&mgr;m2 area is clearly resolved across exposure and focus window.
This paper proposes new scanner fleet management utilizing programmed hotspot patterns.
We have developed a methodology to control and adjust critical parameters of scanner, such as effective illumination
shape and numerical aperture (NA), to obtain the same lithography performance. The purpose is to improve hotspot
patterns and depth of focus (DOF) of each scanner. The method is carried out with a test mask having programmed
hotspot patterns that are likely to become fatal errors for circuit reliability in wafer processing. Actual circuit patterns
whose patterning fidelity is sensitive to the critical parameters are selected as the programmed hotspots. The mask also
has various lithography process monitor marks, such as flare monitor pattern, MEF evaluation pattern and aberration
monitor pattern, for OPE control and simulation. Using the same test mask for every scanner, we can reveal the variation
of lithography performance within a "scanner fleet".
The hotspot patterns on the mask and the patterns printed onto wafers are inspected by Die-to-Database (D2DB) EB
inspection and a wafer D2DB EB inspection, respectively. Using those D2DB inspection systems, we can evaluate
quantitatively the change of pattern shape from drawing data to wafer. The OPE adjustment and OPC feedback are
corrected by using the simulation data acquired for the D2DB inspection. The quality of the evaluation provides accurate
scanner fleet control, resulting in high productivity and cost effectiveness at wafer fabrication.
Mask specifications of the pitch splitting type double patterning for 22nm node and beyond in logic
devices have been discussed. The influences of the mask CD error and the mask induced overlay
error on wafer CD have been investigated in both cases of bright field and dark filed. The
specification for intra-layer overlay alignment is much smaller than inter-layer one. The specification
of mask CD uniformity for dark is more challenging. In order to overcome the technology gap
between single patterning and double patterning, many things will have to be improved.
We have designed the lithography process for 32nm node logic devices under the 1.3NA single exposure
conditions. The simulation and experimental results indicate that the minimum pitches should be
determined as 100nm for line pattern and 120nm for contact hole pattern, respectively. The isolated
feature needs SRAF to pull up the DOF margin. High density SRAM cell with 0.15um<sup>2</sup> area is clearly
resolved across exposure and focus window. The 1.3NA scanner has sufficient focus and overlay stability.
There is no immersion induced defects.
In 45nm-node CMOS, the k1 value is around 0.35. In the low-k1 lithography, the robust design for lens aberration and process fluctuation such as mask CD error is required for manufacturing. The technologies of robust design for 45nm-node CMOS are proposed. The alternating phase shift mask has been applied to obtain high accurate CD controllability for gate level. Since the sensitivity to lens aberration is high, design rule is restricted. Immersion lithography with hyper NA over 1.0 is necessary for contact hole level to get large DOF margin. Since the mask enhanced error factor is large, high accurate CD uniformity on mask is necessary. Using hyper NA immersion tool, high density SRAM whose area is 0.25um2 can be clearly resolved.